View ADV7184_2021802.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

multiformat sdtv video decoder with fast switch overlay support ADV7184 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 analog devices, inc. all rights reserved. features multiformat video decoder supports ntsc-(j, m, 4.43), pal-(b/d/g/h/i/m/n), secam integrates four 54 mhz, 10-bit adcs scart fast blank support clocked from a single 28.63636 mhz crystal line-locked clock-compatible (llc) adaptive digital line length tracking (adllt?), signal processing, and enhanced fifo management give mini tbc functionality 5-line adaptive comb filters proprietary architecture for locking to weak, noisy, and unstable video sources such as vcrs and tuners subcarrier frequency lock an d status information output integrated agc with adaptive peak white mode macrovision? copy protection detection cti (chroma transient improvement) dnr (digital noise reduction) multiple programmable analog input formats cvbs (composite video) s-video (y/c) yprpb component (vesa, mii, smpte, and betacam) 12 analog video input channels integrated antialiasing filters automatic ntsc/pal/secam identification programmable interrupt request output pin digital output formats (8-bit or 16-bit) itu-r bt.656 ycrcb 4:2:2 output + hs, vs, and field 0.5 v to 1.6 v analog signal input range differential gain: 0.5% typ differential phase: 0.5 typ programmable video controls peak white/hue/brightness/saturation/contrast integrated on-chip video timing generator free-run mode (generates stable video output with no i/p) vbi decode support for closed captioning (including xds), wss, cgms, gemstar? 1/2, teletext, vitc, vps power-down mode 2-wire serial mpu interface (i 2 c?-compatible) 3.3 v analog, 1.8 v digital core; 3.3 v io supply industrial temperature grade: C40c to +85c 80-lead lqfp pb-free package applications dvd recorders video projectors hdd-based pvrs/dvdrs lcd tvs set-top boxes security systems digital televisions avr receivers general description the ADV7184 integrated video decoder automatically detects and converts a standard analog baseband television signal, which is compatible with worldwide standards ntsc, pal, and secam, into 4:2:2 component video data-compatible with 16-bit or 8-bit ccir601/ccir656. the advanced and highly flexible digital output interface enables performance video decoding and conversion in line- locked clock-based systems. this makes the device ideally suited for a broad range of applications with diverse analog video characteristics, including tape-based sources, broadcast sources, security and surveillance cameras, and professional systems. the 10-bit accurate adc provides professional quality video performance and is unmatched. this allows true 8-bit resolution in the 8-bit output mode. the 12 analog input channels accept standard composite, s-video, and yprpb video signals in an extensive number of combinations. agc and clamp restore circuitry allow an input video signal peak-to-peak range of 0.5 v to 1.6 v. alternatively, these can be bypassed for manual settings. the fixed 54 mhz clocking of the adcs and datapath for all modes allows very precise, accurate sampling and digital filtering. the line locked clock output allows the output data rate, timing signals, and output clock signals to be synchronous, asynchronous, or line locked even with 5% line length variation. the output control signals allow glueless interface connections in almost any application. the ADV7184 modes are set up over a 2-wire, serial, bidirectional port (i 2 c- compatible). scart and overlay functionality are enabled by the ADV7184s ability to simultaneously process cvbs and standard definition rgb signals. signal mixing is controlled by the fast blank pin. the ADV7184 is fabricated in a 3.3 v cmos process. its monolithic cmos construction ensures greater functionality with lower power dissipation. the ADV7184 is packaged in a small 80-lead lqfp pb-free package.
ADV7184 rev. 0 | page 2 of 108 table of contents introduction ...................................................................................... 4 analog front end ......................................................................... 4 standard definition processor (sdp)........................................ 4 electrical characteristics ................................................................. 5 video specifications..................................................................... 6 timing specifications .................................................................. 7 analog specifications................................................................... 7 thermal specifications ................................................................ 8 timing diagrams.......................................................................... 8 absolute maximum ratings............................................................ 9 package thermal performance................................................... 9 esd caution.................................................................................. 9 pin configuration and function descriptions........................... 10 analog front end ........................................................................... 12 analog input muxing ................................................................ 12 manual input muxing................................................................ 14 xtal clock input pin functionality....................................... 15 28.63636 mhz crysta l operation ............................................ 15 antialiasing filters ..................................................................... 15 scart and fast blanking......................................................... 15 fast blank control...................................................................... 16 readback of fb pin status......................................................... 18 global control registers ............................................................... 19 power-save modes...................................................................... 19 reset control .............................................................................. 19 global pin control ..................................................................... 19 global status registers................................................................... 21 standard definition processor (sdp).......................................... 22 sd luma path ............................................................................. 22 sd chroma path......................................................................... 22 sync processing........................................................................... 23 vbi data recovery..................................................................... 23 general setup.............................................................................. 23 color controls ............................................................................ 25 clamp operation........................................................................ 27 luma filter .................................................................................. 28 chroma filter.............................................................................. 31 gain operation........................................................................... 31 chroma transient improvement (cti) .................................. 34 digital noise reduction (dnr), and luma peaking filter .. 35 comb filters................................................................................ 36 av code insertion and controls ............................................. 39 synchronization output signals............................................... 40 sync processing .......................................................................... 48 vbi data decode ....................................................................... 48 i 2 c readback registers ............................................................... 57 pixel port configuration ............................................................... 71 mpu port description................................................................... 72 register accesses ........................................................................ 73 register programming............................................................... 73 i 2 c sequencer.............................................................................. 73 i 2 c register maps ........................................................................... 74 user map ..................................................................................... 74 user sub map.............................................................................. 90 i 2 c programming examples.......................................................... 99 mode 1 cvbs input................................................................... 99 mode 2 s-video input ............................................................. 100 mode 3 525i/625i yprpb input .............................................. 101 mode 4 scarts-video or cvbs autodetect .................. 102 mode 5 scart fast blankcvbs and rgb...................... 103 mode 6 scart rgb input (static fast blank)cvbs and rgb ............................................................................................ 104
ADV7184 rev. 0 | page 3 of 108 pcb layout recommendations ................................................. 105 analog interface inputs........................................................... 105 power supply decoupling ....................................................... 105 pll ............................................................................................. 105 digital outputs (both data and clocks) .............................. 105 digital inputs............................................................................. 106 xtal and load capacitor values selection ........................ 106 typical circuit connection ......................................................... 107 outline dimensions...................................................................... 108 ordering guide ......................................................................... 108 revision history 7/05revision 0: initial version
ADV7184 rev. 0 | page 4 of 108 introduction the ADV7184 is a high quality, single chip, multiformat video decoder that automatically detects and converts pal, ntsc, and secam standards in the form of composite, s-video, and component video into a digital itu-r bt.656 format. the advanced and highly flexible digital output interface enables performance video decoding and conversion in line-locked clock-based systems. this makes the device ideally suited for a broad range of applications with diverse analog video charac- teristics, including tape-based sources, broadcast sources, security and surveillance cameras, and professional systems. analog front end the ADV7184 analog front end includes four 10-bit adcs that digitize the analog video signal before applying it to the standard definition processor. the analog front end uses differential channels to each adc to ensure high performance in mixed-signal applications. the front end also includes a 12-channel input mux that enables multiple video signals to be applied to the ADV7184. current and voltage clamps are positioned in front of each adc to ensure that the video signal remains within the range of the converter. fine clamping of the video signals is performed downstream by digital fine clamping within the ADV7184. the adcs are configured to run in 4 oversampling mode. the ADV7184 has optional antialiasing filters on each of the four input channels. the filters are designed for sd video with approximately 6 mhz bandwidth. scart and overlay functionality are enabled by the ADV7184s ability to simultaneously process cvbs and standard definition rgb signals. signal mixing is controlled by the fast blank pin. standard definition processor (sdp) the ADV7184 is capable of decoding a large selection of baseband video signals in composite, s-video, and component formats. the video standards supported include pal b/d/i/g/h, pal60, pal m, pal n, pal nc, ntsc m/j, ntsc 4.43, and secam b/d/g/k/l. the ADV7184 can automatically detect the video standard and process it accordingly. the ADV7184 has a 5-line, superadaptive, 2d comb filter that gives superior chrominance and luminance separation when decoding a composite video signal. this highly adaptive filter automatically adjusts its processing mode according to video standard and signal quality without user intervention. video user controls such as brightness, contrast, saturation, and hue are also available within the ADV7184. the ADV7184 implements a patented adaptive digital line- length tracking (adllt) algorithm to track varying video line lengths from sources such as a vcr. adllt enables the ADV7184 to track and decode poor quality video sources such as vcrs, noisy sources from tuner outputs, vcd players, and camcorders. the ADV7184 contains a chroma transient improvement (cti) processor that sharpens the edge rate of chroma transitions, resulting in sharper vertical transitions. the ADV7184 can process a variety of vbi data services, such as closed captioning (cc), wide screen signaling (wss), copy generation management system (cgms), gemstar 1/2, extended data service (xds), and teletext. the ADV7184 is fully macrovision certified; detection circuitry enables type i, ii, and iii protection levels to be identified and reported to the user. the decoder is also fully robust to all macrovision signal inputs. functional block diagram cvbs s-video yprpb scart - (rgb + cvbs) a/d anti alias filter 10 a/d anti alias filter 10 a/d anti alias filter 10 a/d anti alias filter 10 ain1? ain12 12 input mux data preprocessor luma filter sync extract chroma filter luma resample resample control f sc recovery chroma resample chroma demod colorspace conversion luma 2d comb (5h max) chroma 2d comb (4h max) cvbs decimation and downsampling filters 10 10 10 10 cr y cb clamp clamp clamp clamp fast blank overlay control and av code insertion vbi data recovery macrovision detection global control standard autodetection synthesized llc control free run output control 16 standard definition processor r g b cr cb c 8 8 pixel data p15-p8 p7-p0 hs sfl llc2 llc1 field vs int output formatter control and data fb sync processing and clock generation serial interface control and vbi data sync and clk control ADV7184 05479-001 y cr cb cvbs/y sclk sda alsb figure 1.
ADV7184 rev. 0 | page 5 of 108 electrical characteristics at a vdd = 3.15 v to 3.45 v, d vdd = 1.65 v to 2.0 v, d vddio = 3.0 v to 3.6 v, p vdd = 1.71 v to 1.89 v, nominal input range 1.6 v. operating temperature range, unless otherwise noted. table 1. parameter symbol test conditions min typ max unit static performance 1, 2, 3 resolution (each adc) n 10 bits integral nonlinearity inl bsl at 54 mhz C0.6/+0.7 3 lsb differential nonlinearity dnl bsl at 54 mhz ?0.5/+0.5 -0.99/2.5 lsb digital inputs input high voltage 4 v ih 2 v input low voltage 5 v il 0.8 v input current i in pins listed in note 6 C50 +50 a all other pins 7 C10 +10 a input capacitance 9 c in 10 pf digital outputs output high voltage 8 v oh i source = 0.4 ma 2.4 v output low voltage 8 v ol i sink = 3.2 ma 0.4 v high impedance leakage current i leak 10 a output capacitance 9 c out 20 pf power requirements 9 digital core power supply d vdd 1.65 1.8 2 v digital i/o power supply d vddio 3.0 3.3 3.6 v pll power supply p vdd 1.71 1.8 1.89 v analog power supply a vdd 3.15 3.3 3.45 v digital core supply current i dvdd 105 ma digital i/o supply current i dvddio 4 ma pll supply current i pvdd 11 ma analog supply current i avdd cvbs input 10 99 ma yprpb input 11 269 ma power-down current i pwrdn 0.65 ma power-up time t pwrup 20 ms 1 all adc linearity tests performed at input range of full scale C 12.5%, and at zero scale +12.5%. 2 max inl and dnl specifications obtained wi th part configured for co mponent video input. 3 temperature range t min to t max , C40c to +85c. the min/max specific ations are guaranteed over this range. 4 to obtain specified v ih level on pin 29, register 0x13 (write on ly) must be programmed with value 0x04. if register 0x13 is programmed with value 0x00 , then v ih on pin 29 = 1.2 v. 5 to obtain specified v il level on pin 29, register 0x13 (write on ly) must be programmed with value 0x04. if register 0x13 is programmed with value 0x00 , then v il on pin 29 = 0.4 v. 6 pins: 36 and 79. 7 excluding all test pi ns (test0 to test12) 8 v oh and v ol levels obtained using default drive strength value (0xd5) in register subaddress 0xf4. 9 guaranteed by characterization. 10 adc0 powered on only. 11 all four adcs powered on.
ADV7184 rev. 0 | page 6 of 108 video specifications at a vdd = 3.15 v to 3.45 v, d vdd = 1.65 v to 2.0 v, d vddio = 3.0 v to 3.6 v, p vdd = 1.71 v to 1.89 v. operating temperature range, unless otherwise noted. table 2. parameter 1, 2 symbol test conditions min typ max unit nonlinear specifications differential phase dp cvbs i/p, modulate 5-step 0.5 0.7 degree differential gain dg cvbs i/p, modulate 5-step 0.5 0.7 % luma nonlinearity lnl cvbs i/p, 5-step 0.5 0.7 % noise specifications snr unweighted luma ramp 54 56 db luma flat field 56 58 db analog front end crosstalk 60 db lock time specifications horizontal lock range C5 +5 % vertical lock range 40 70 hz fsc subcarrier lock range 1.3 hz color lock in time 60 lines sync depth range 3 20 200 % color burst range 5 200 % vertical lock time 2 fields autodetection switch speed 100 lines chroma specifications hue accuracy hue 1 degree color saturation accuracy cl_ac 1 % color agc range 5 400 % chroma amplitude error 0.5 % chroma phase error 0.4 degree chroma luma intermodulation 0.2 % luma specifications luma brightness accuracy cvbs, 1 v i/p 1 % luma contrast accuracy cvbs, 1 v i/p 1 % 1 temperature range t min to t max , C40c to +85c. the min/max specific ations are guaranteed over this range. 2 guaranteed by characterization. 3 nominal sync depth is 300 mv at 100% sync depth range.
ADV7184 rev. 0 | page 7 of 108 timing specifications at a vdd = 3.15 v to 3.45 v, d vdd = 1.65 v to 2.0 v, d vddio = 3.0 v to 3.6 v, p vdd = 1.71 v to 1.89 v. operating temperature range, unless otherwise noted. table 3. parameter 1, 2 symbol test conditions min typ max unit system clock and crystal nominal frequency 28.63636 mhz frequency stability 50 ppm i 2 c port 3 sclk frequency 400 khz sclk min pulse width high t 1 0.6 s sclk min pulse width low t 2 1.3 s hold time (start condition) t 3 0.6 s setup time (start condition) t 4 0.6 s sda setup time t 5 100 ns sclk and sda rise time t 6 300 ns sclk and sda fall time t 7 300 ns setup time for stop condition t 8 0.6 s reset feature reset pulse width 5 ms clock outputs llc1 mark space ratio t 9 :t 10 45:55 55:45 % duty cycle llc1 rising to llc2 rising t 11 1 ns llc1 rising to llc2 falling t 12 1 ns data and control outputs data output transitional time 4 t 13 negative clock edge to start of valid data; (t access = t 10 C t 13 ) 3.6 ns data output transitional time 4 t 14 end of valid data to negative clock edge; (t hold = t 9 + t 14 ) 2.4 ns propagation delay to hi-z t 15 6 ns max output enable access time t 16 7 ns min output enable access time t 17 4 ns 1 temperature range t min to t max , C40c to +85c. the min/max specific ations are guaranteed over this range. 2 guaranteed by characterization. 3 ttl input values are 0 v to 3 v, with rise/fall times 3 ns, measured between the 10% and 90% points. 4 timing figures obtained using de fault drive strength value (0xd5) in register subaddress 0xf4. analog specifications at a vdd = 3.15 v to 3.45 v, d vdd = 1.65 v to 2.0 v, d vddio = 3.0 v to 3.6 v, p vdd = 1.71 v to 1.89 v. operating temperature range, unless otherwise noted. recommended analog input video si gnal range: 0.5 v to 1.6 v, typically 1 v p-p. table 4. parameter 1 , 2 symbol test conditions min typ max unit clamp circuitry external clamp capacitor 0.1 f input impedance 3 clamps switched off 10 m input impedance of pin 40 (fb) 20 k large clamp source current 0.75 ma large clamp sink current 0.75 ma fine clamp source current 17 a fine clamp sink current 17 a 1 temperature range t min to t max , C40c to +85c. the min/max specific ations are guaranteed over this range. 2 guaranteed by characterization. 3 except pin 40 (fb).
ADV7184 rev. 0 | page 8 of 108 thermal specifications table 5. parameter symbol test conditions min typ max unit junction-to-case thermal resistance jc 4-layer pcb with solid ground plane 7.6 c/w junction-to-ambient thermal resistance (still air) ja 4-layer pcb with solid ground plane 38.1 c/w timing diagrams 05479-002 sda sclk t 3 t 5 t 3 t 4 t 8 t 6 t 7 t 2 t 1 figure 2. i 2 c timing output llc 1 output llc 2 05479-003 outputs p0?p15, vs, hs, field, sfl t 9 t 11 t 10 t 14 t 13 t 12 figure 3. pixel port and control output timing 05479-004 oe p0?p15, hs, vs, field, sfl t 15 t 16 t 17 figure 4. oe timing
ADV7184 rev. 0 | page 9 of 108 absolute maximum ratings table 6. parameter rating a vdd to agnd 4 v d vdd to dgnd 2.2 v p vdd to agnd 2.2 v d vddio to dgnd 4 v d vddio to avdd C0.3 v to +0.3 v p vdd to d vdd C0.3 v to +0.3 v d vddio to p vdd C0.3v to +2 v d vddio to d vdd C0.3v to +2 v a vdd to p vdd C0.3v to +2 v a vdd to d vdd C0.3v to +2 v digital inputs voltage to dgnd C0.3v to d vddio + 0.3 v digital output voltage to dgnd C0.3v to d vddio + 0.3 v analog inputs to agnd agnd C 0.3 v to a vdd + 0.3 v maximum junction temperature (t j max) 125c storage temperature range C65c to +150c infrared reflow soldering (20 sec) 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal performance to reduce power consumption the user is advised to turn off any unused adcs when using the part. the junction temperature must always stay below the maximum junction temperature (t j max) of 125c. the following equation shows how to calculate the junction temperature: t j = t a max + ( ja w max ) where: t a max = 85c. ja = 30c/w. w max = (( a vdd i av d d ) + ( d vdd i dvdd ) + ( d vddio i dvddio ) + ( p vdd i pvdd )). esd caution esd (electrostatic discharge) sensiti ve device. electrostatic charges as hi gh as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ADV7184 rev. 0 | page 10 of 108 pin configuration and fu nction descriptions 2 hs 3 dgnd 4 dvddio 7 p9 6 p10 5 p11 1 vs 8 p8 9 dgnd 10 dvdd 12 sfl 13 test2 14 dgnd 15 dvddio 16 test8 17 test12 18 test11 19 p7 20 p6 11 int 59 58 57 54 55 56 60 53 52 ain11 ain4 ain10 capc1 capc2 agnd ain5 agnd cml 51 refout 49 capy2 48 capy1 47 agnd 46 ain3 45 ain9 44 ain2 43 ain8 42 ain1 41 ain7 50 avdd 21 p5 22 p4 23 p3 24 p2 25 test3 26 llc2 27 llc1 28 xtal1 29 xtal 30 dvdd 31 dgnd 32 p1 33 p0 34 test10 35 test9 36 pwrdn 37 elpf 38 pvdd 39 agnd 40 fb 80 field 79 oe 78 test1 77 test6 76 p12 75 p13 74 p14 73 p15 72 dvdd 71 dgnd 70 test0 69 test4 68 sclk 67 sda 66 alsb 65 test7 64 reset 63 test5 62 ain6 61 ain12 pin 1 ADV7184 top view (not to scale) 05479-005 figure 5. 80-lead lqfp pin configuration table 7. pin function descriptions pin no. mnemonic type function 3, 9, 14, 31, 71 dgnd g digital ground. 39, 47, 53, 56 agnd g analog ground. 4, 15 dvddio p digital i/o supply voltage (3.3 v). 10, 30, 72 dvdd p digital core supply voltage (1.8 v). 50 avdd p analog supply voltage (3.3 v). 38 pvdd p pll supply voltage (1.8 v). 42, 44, 46, 58, 60, 62, 41, 43, 45, 57, 59, 61 ain1 to ain12 i analog video input channels. 11 int o interrupt request output. interr upt occurs when certain signal s are detected on the input video. see the user sub map register details in table 103. 40 fb i fast blank. fb is a fast switch overlay input that switches between cvbs and rgb analog i/p signals. 70, 78, 13, 25, 69, 63, 35, 34, 18, 17 test0 to test5, test9 to test12 leave these pins unconnected. 77, 65 test6 to test7 tie to agnd 16 test8 tie to dvddio 33, 32, 24, 23, 22, 21, 20, 19, 8, 7, 6, 5, 76, 75, 74, 73 p0 to p15 o video pixel output port. 2 hs o horizontal synchronization output signal. 1 vs o vertical synchronization output signal. 80 field o field synchronization output signal.
ADV7184 rev. 0 | page 11 of 108 pin no. mnemonic type function 67 sda i/o i 2 c port serial data input/output pin. 68 sclk i i 2 c port serial clock input (max clock rate of 400 khz). 66 alsb i this pin selects the i 2 c address for the ADV7184. alsb set to logic 0 sets the address for a write as 0x40; set to logic 1 sets the address as 0x42. 64 reset i system reset input, active low. a minimum low reset pulse width of 5 ms is required to reset the ADV7184 circuitry. 27 llc1 o line-locked clock 1. line-locked output cloc k for the pixel data output by the ADV7184. nominally 27 mhz, but varies up or do wn according to video line length. 26 llc2 o line-locked clock 2. this is a divide-by-2 versi on of the llc1 output clock for the pixel data output by the ADV7184. nominally 13.5 mhz, b ut varies up or down according to video line length. 29 xtal i this is the input pin for the 28. 63636 mhz crystal, or can be overdriven by an external 3.3 v, 28.63636 mhz clock oscillator source. in crysta l mode, the crystal must be a fundamental crystal. 28 xtal1 o this pin should be connected to the 28.63636 mh z crystal or left as a no connect if an external 3.3 v, 28.63636 mhz clock oscillator sour ce is used to clock the ADV7184. in crystal mode, the crystal must be a fundamental crystal. 36 pwrdn i logic 0 on this pin places the adv 7184 in a power-down mode. refer to the i 2 c register maps section for more options on power-down modes for the ADV7184. 79 oe i when set to logic 0, oe enables the pixel output bus, p15 to p0 of the ADV7184. logic 1 on the oe pin places p15 through p0, hs, vs , and sfl/sync_out into a high impedance state. 37 elpf i the recommended external loop filter must be connected to this elpf pin, as shown in figure 50. 12 sfl o subcarrier frequency lock. this pin contains a serial output stream that can be used to lock the subcarrier frequency when this decode r is connected to any analog devices, inc. digital video encoder. 51 refout o internal voltage refere nce output. refer to figure 50 for a recommended capacitor network for this pin. 52 cml o the cml pin is a common-mode level for the internal adcs. refer to figure 50 for a recommended capacitor network for this pin. 48, 49 capy1, capy2 i adcs capacitor network. refer to figure 50 for a recommended capacitor network for these pins. 54, 55 capc1, capc2 i adcs capacitor network. refer to figure 50 for a recommended capacitor network for these pins.
ADV7184 rev. 0 | page 12 of 108 analog front end analog input muxing ain1 ain7 ain2 ain8 ain3 ain9 ain4 ain10 ain5 ain11 ain6 ain12 ain3 ain4 ain2 ain9 ain7 ain8 ain4 ain5 ain10 ain11 ain5 ain6 ain11 ain6 ain4 ain12 ain12 ain1 ain7 ain2 ain8 ain3 ain9 ain4 ain10 ain5 ain11 ain6 ain12 1 0 adc2_sw[3:0] adc2 1 0 adc3_sw[3:0] adc3 1 0 adc1_sw[3:0] adc1 1 0 adc0_sw[3:0] adc0 adc_sw_man_en sdm_sel[1:0] prim_mode[3:0] insel[3:0] rgb_ip_sel internal mapping functions 05479-006 figure 6. internal pin connections the ADV7184 has an integrated analog muxing section that allows connecting more than one source of video signal to the decoder. figure 6 outlines the overall structure of the input muxing provided in the ADV7184. as seen in figure 6, the analog input muxes can be controlled in two ways: ? by functional registers (insel). using insel[3:0] simplifies the setup of the muxes, and minimizes crosstalk between channels by pre-assigning the input channels. this is referred to as adi-recommended input muxing. ? by an i 2 c manual override (adc_sw_man_en, adc0_sw, adc1_sw, adc2_sw, adc3_sw). this is provided for applications with special requirements, such as number/combinations of signals, which would not be served by the pre-assigned input connections. this is referred to as manual input muxing. refer to figure 7 for an overview of the two methods of controlling input muxing. 05479-007 set sdm_sel[1:0] and insel[3:0] to configure ADV7184 to decode video format: cvbs: 00, 0000 yc: 00, 0110 yprpb: 00, 1001 scart (cvbs/rgb): 00, 1111 set sdm_sel[1:0] for s-video/cvbs autodetect use manual input muxing (adc_sw_man_en, adc0_sw, adc1_sw, adc2_sw, adc3_sw) set sdm_sel[1:0] and insel[3:0] for required muxing configuration connecting analog signals to ADV7184 adi recommended input muxing; see tables 8 and 9 no yes figure 7. input muxing overview
ADV7184 rev. 0 | page 13 of 108 adi recommended input muxing a maximum of 12 cvbs inputs can be connected and decoded by the ADV7184. as seen in figure 5, this means the sources must be connected to adjacent pins on the ic. this calls for a careful design of the pcb layout, for example, ground shielding between all signals routed through tracks that are physically close together. sdm_sel[1:0], s-video and cvbs autodetect mode select, address 0x69 [1:0] the sdm_sel bits decide on input routing and whether insel[3:0] is used to govern i/p routing decision. the cvbs/yc autodetection feature is enabled using sdm_sel = 11. table 8. sdm_sel[1:0] sdm_sel[1:0] mode analogue video inputs 00 as per insel[3:0] as per insel[3:0] 01 cvbs ain11 10 yc y = ain10 c = ain12 11 yc/cvbs auto cvbs = ain11 y = ain11 c = ain12 insel[3:0] input selection, address 0x00 [3:0] the insel bits allow the user to select an input channel as well as the input format. depending on the pcb connections, only a subset of the insel modes is valid. the insel[3:0] not only switches the analog input muxing, it also configures the standard definition processor core to process cvbs (comp), s-video (y/c), or component (ypbpr/rgb) format. adi-recommended input muxing is designed to minimize crosstalk between signal channels and to obtain the highest level of signal integrity. table 10 summarizes how the pcb layout should connect analog video signals to the ADV7184. it is strongly recommended to connect any unused analog input pins to agnd to act as a shield. connect inputs ain7 to ain11 to agnd when only six input channels are used. this improves the quality of the sampling due to better isolation between the channels. ain12 is not under the control of insel[3:0]. it can be routed to adc0/adc1/adc2 only by manual muxing. see table 11 for details. table 9. input channel switching using insel[3:0] description insel[3:0] analog input pins video format 0000 (default) cvbs1 = ain1 b = ain4 or ain7 1 r = ain5 or ain8 1 g = ain6 or ain9 1 scart (cvbs and r, g, b) 0001 cvbs2 = ain2 b = ain4 or ain7 1 r = ain5 or ain8 1 g = ain6 or ain9 1 scart (cvbs and r, g, b) 0010 cvbs3 = ain3 b = ain4 or ain7 1 r = ain5 or ain8 1 g = ain6 or ain9 1 scart (cvbs and r, g, b) 0011 cvbs4 = ain4 b = ain7 r = ain8 g = ain9 scart (cvbs and r, g, b) 0100 cvbs1 = ain5 b = ain7 r = ain8 g = ain9 scart (cvbs and r, g, b) 0101 cvbs1 = ain6 b = ain7 r = ain8 g = ain9 scart (cvbs and r, g, b) 0110 y1 = ain1 c1 = ain4 yc 0111 y2 = ain2 c2 = ain5 yc description insel[3:0] analog input pins video format 1000 y3 = ain3 c3 = ain6 yc 1001 y1 = ain1 pb1 = ain4 pr1 = ain5 yprpb 1010 y2 = ain2 pb2 = ain3 pr2 = ain6 yprpb 1011 cvbs7 = ain7 b = ain4 r = ain5 g = ain6 scart (cvbs and r, g, b) 1100 cvbs8 = ain8 b = ain4 r = ain5 g = ain6 scart (cvbs and r, g, b) 1101 cvbs9 = ain9 b = ain4 r = ain5 g = ain6 scart (cvbs and r, g, b) 1110 cvbs10 = ain10 b = ain4 or ain7 1 r = ain5 or ain8 1 g = ain6 or ain9 1 scart (cvbs and r, g, b) 1111 cvbs11 = ain11 b = ain4 or ain7 1 r = ain5 or ain8 1 g = ain6 or ain9 1 scart (cvbs and r, g, b) 1 selectable via rgb_ip_sel.
ADV7184 rev. 0 | page 14 of 108 rgb_ip_sel, address 0xf1 [0] for scart input, r, g and b signals can be input on either ain4, ain5, and ain6 or on ain7, ain8, and ain9. 0 (default)b is input on ain4, r is input on ain 5, and g is input on ain6. 1b is input on ain7, r is input on ain 8, and g is input on ain9. manual input muxing by accessing a set of manual override muxing registers, the analog input muxes of the ADV7184 can be controlled directly. this is referred to as manual input muxing. manual input muxing overrides other input muxing control bits, for example, insel. manual muxing is activated by setting the adc_sw_man_en bit. it affects only the analog switches in front of the adcs. this means if the settings of insel and the manual input muxing registers (adc0/adc1/acd2/adc3_sw) contradict each other, the adc0/adc1/adc2 /adc3_sw settings apply and insel is ignored. manual input muxing controls only the analog input muxes. insel[3:0] still has to be set so the follow-on blocks process the video data in the correct format. this means insel must still be used to tell the ADV7184 whether the input signal is of component, yc, or cvbs format. restrictions in the channel routing are imposed by the analog signal routing inside the ic; every input pin cannot be routed to each adc. refer to figure 6 for an overview on the routing capabilities inside the chip. the four mux sections can be controlled by the reserved control signal buses adc0/adc1/ adc2/adc3_sw[3:0]. table 11 explains the control words used. table 10. input channel assignments input channel pin no. adi-recommended input muxing control insel[3:0] ain7 41 cvbs7 scart1-b ain1 42 cvbs1 yc1-y yprpb1-y scart2-cvbs ain8 43 cvbs8 scart1-r ain2 44 cvbs2 yc2-y yprpb2-y ain9 45 cvbs9 scart1-g ain3 46 cvbs3 yc3-y yprpb2-pb ain10 57 cvbs10 ain4 58 cvbs4 yc1-c yprpb1-pb scart2-b ain11 59 cvbs11 scart1-cvbs ain5 60 cvbs5 yc2-c yprpb1-pr scart2-r ain12 61 not available ain6 62 cvbs6 yc3-c yprpb2-pr scart2-g table 11. manual mux settings for all adcs (adc_sw_man_en = 1) adc0_sw[3:0] adc0 connected to adc1_sw[3:0] adc1 connected to adc2_sw[3:0] adc2 connected to adc3_sw[3:0] adc3 connected to 0000 no connection 0000 no connection 0000 no connection 0000 no connection 0001 ain1 0001 no connection 0001 no connection 0001 no connection 0010 ain2 0010 no connection 0010 ain2 0010 no connection 0011 ain3 0011 ain3 0011 no connection 0011 no connection 0100 ain4 0100 ain4 0100 no connection 0100 ain4 0101 ain5 0101 ain5 0101 ain5 0101 no connection 0110 ain6 0110 ain6 0110 ain6 0110 no connection 0111 no connection 0111 no connection 0111 no connection 0111 no connection 1000 no connection 1000 no connection 1000 no connection 1000 no connection 1001 ain7 1001 no connection 1001 no connection 1001 ain7 1010 ain8 1010 no connection 1010 ain8 1010 no connection 1011 ain9 1011 ain9 1011 no connection 1011 no connection 1100 ain10 1100 ain10 1100 no connection 1100 no connection 1101 ain11 1101 ain11 1101 ain11 1101 no connection 1110 ain12 1110 ain12 1110 ain12 1110 no connection 1111 no connection 1111 no connection 1111 no connection 1111 no connection
ADV7184 rev. 0 | page 15 of 108 adc_sw_man_en, manual input muxing enable, address 0xc4 [7] adc0_sw[3:0], adc0 mux configuration, address 0xc3 [3:0] adc1_sw[3:0], adc1 mux configuration, address 0xc3 [7:4] adc2_sw[3:0], adc2 mux configuration, address 0xc4 [3:0] adc3_sw[3:0], adc3 mux configuration, address 0xf3 [7:4] see table 11. xtal clock input pin functionality xtal_ttl_sel, address 0x13 [2] the xtal pad is normally part of the crystal oscillator circuit, powered from a 1.8 v supply. for optimal clock generation, the slice level of the input buffer of this circuit is at approximately half the supply voltage. this makes it incompatible with tll level signals. 0 (default)a crystal is used to generate the ADV7184s clock. 1an external ttl level clock is supplied. a different input buffer can be selected, which slices at ttl-compatible levels. this inhibits operation of the crystal oscillator and, therefore, can only be used when a clock signal is applied. 28.63636 mhz crystal operation en28xtal, address 0x1d [6] the ADV7184 can operate on two different base crystal frequencies. selecting one over the other can be desirable in systems in which board crosstalk between different components leads to undesirable interference between video signals. it is recommended by adi to use an xtal of frequency 28.63636 mhz to clock the ADV7184. the programming examples at the end of this datasheet presume 28.63636 mhz crystal is used. 0 (default)xtal frequency is 27 mhz. 1xtal frequency is 28.63636 mhz. antialiasing filters the ADV7184 has optional antialiasing filters on each of the four input channels. the filters are designed for sd video with approximately 6 mhz bandwidth. a plot of the filter response is shown in figure 8. the filters can be individually enabled via i 2 c under the control of aa_filt_en[3:0]. aa_filt_en[0], address 0xf3 [0] 0 (default)the filter on channel 0 is disabled. 1the filter on channel 0 is enabled. aa_filt_en[1], address 0xf3 [1] 0 (default)the filter on channel 1 is disabled. 1the filter on channel 1 is enabled. aa_filt_en[2], address 0xf3 [2] 0 (default)the filter on channel 2 is disabled. 1the filter on channel 2 is enabled. aa_filt_en[3], address 0xf3 [3] 0 (default)the filter on channel 3 is disabled. 1the filter on channel 3 is enabled. 1m 1g 05479-008 frequency (hz) attenuation (db) 0 ?2 ?4 ?6 ?8 ?10 ?12 ?14 ?16 ?20 ?24 ?28 ?32 ?18 ?22 ?26 ?30 ?34 ?36 ?38 ?40 ?42 ?44 ?46 ?48 ?50 10m 100m ?52 response of aa filter with calibrated capacitors figure 8. frequency response of in ternal ADV7184 antialiasing filters scart and fast blanking the ADV7184 can support simultaneous processing of cvbs and rgb standard definition signals to enable scart compatibility and overlay functionality. this function is available when insel[3:0] is set appropriately (see table 9). timing extraction is always performed by the ADV7184 on the cvbs signal. however, a combination of the cvbs and rgb inputs can be mixed and output under control of i 2 c registers and the fast blank (fb) pin. four basic modes are supported: static switch mode the fb pin is not used. the timing is extracted from the cvbs signal, and either the cvbs content or rgb content can be output under the control of cvbs_rgb_sel. this mode allows the selection of a full-screen picture from either source. overlay is not possible in static switch mode. fixed alpha blending the fb pin is not used. the timing is extracted from the cvbs signal, and an alpha blended combination of the video from the cvbs and rgb sources is output. this alpha blending is applied to the full screen. the alpha blend factor is selected with the i 2 c signal man_alpha[6:0] . overlay is not possible in fixed alpha blending mode.
ADV7184 rev. 0 | page 16 of 108 dynamic switching (fast mux) source selection is under the control of the fast blank (fb) pin. this enables dynamic multiplexing between the cvbs and rgb sources. with default settings, when logic 1 is applied to the fb pin the rgb source is selected; when logic 0 is applied to the fb pin the cvbs source is selected. this mode is suitable for the overlay of subtitles, teletext, or other material. typically, the cvbs source carries the main picture and the rgb source has the overlay data. dynamic switching with edge-enhancement this provides the same functionality as the dynamic switching mode, but with adi proprietary edge-enhancement algorithms that improve the visual appearance of transitions for signals from a wide variety of sources. system diagram a block diagram of the ADV7184 fast blanking configuration is shown in figure 9. the cvbs signal is processed by the ADV7184 and converted to yprpb. the rgb signals are processed by a color space converter (csc) and samples are converted to yprpb. both sets of yprpb signals are input to the sub-pixel blender, which can be configured to operate in any of the four modes outlined above. the fast blank position resolver determines the time position of the fb to a very high accuracy (<1 ns); this position infor- mation is then used by the sub-pixel blender in dynamic switching modes. this enables the ADV7184 to implement high performance multiplexing between the cvbs and rgb sources, even when the rgb data source is completely asynchronous to the sampling crystal reference. an antialiasing filter is required on all four data channels (r, g, b, and cvbs). the order of this filter is reduced as all of the signals are sampled at 54 mhz. the switched or blended data is output from the ADV7184 in the standard output formats (see table 99). fast blank control fb_mode[1:0], address 0xed [1:0] fb_mode controls which of the fast blank modes is selected. table 12. fb_mode[1:0] function fb_mode[1:0] description 00 (default) static switch mode. 01 fixed alpha blending. 10 dynamic switching (fast mux). 11 dynamic switching with edge enhancement. static mux selection control cvbs_rgb_sel, address 0xed [2] cvbs_rgb_sel controls whether the video from the cvbs or the rgb source is selected for output from the ADV7184. 0 (default)data from the cvbs source is selected for output. 1data from the rgb source is selected for output. alpha blend coefficient man_alpha_val[6:0], address 0xee [6:0] when fb_mode[1:0] = 01 and fixed alpha blending is selected, man_alpha_val[6:0] determines the proportion in which the video from the cvbs source and the rgb source are blended. equation 1 shows how these bits affect the video output. 64 ] 0 : 6 [ _ _ 64 ] 0 : 6 [ _ _ 1 val alpha man video val alpha man video video rgb cvbs out + ? ? ? ? ? ? ? = (1) the maximum valid value for man_alpha_val[6:0] is 1000000 such that the alpha blender coefficients remain between 0 and 1. the default value for man_alpha_val[6:0] is 0000000. adc1 r adc0 cvbs adc2 g adc3 b fast blank position resolver fast blank (fb pin) i 2 c control output formatter yprpb subpixel blender signal conditioning clamping and decimation timing extraction video processing signal conditioning clamping and decimation rgb yprpb conversion 05479-009 figure 9. fast blank block diagram
ADV7184 rev. 0 | page 17 of 108 fast blank edge shaping fb_edge_shape[2:0], address 0xef [2:0] to improve the picture transition for high speed fast blank switching, an edge shape mode is available on the ADV7184. depending on the format of the rgb inputs, it may be advantageous to apply this scheme to different degrees. the levels are selected via the fb_edge_shape[2:0] bits. users are advised to try each of the settings and select the setting that is most visually pleasing in their system. table 13. fb_edge_shape[2:0] function fb_edge_shape[2:0] description 000 no edge shaping. 001 level 1 edge shaping. 010 (default) level 2 edge shaping. 011 level 3 edge shaping. 100 level 4 edge shaping. 101 to 111 not valid. contrast reduction for overlay applications, text can be more readable if the contrast of the video directly behind the text is reduced. to enable the definition of a window of reduced contrast behind inserted text, the signal applied to the fb pin can be interpreted as a tri-level signal, as shown in figure 10. cvbs source 100% cvbs source 50% contras t rgb source 100% sandcastle 05479-010 figure 10. fast blank signal representation with contrast reduction enabled contrast reduction enable cntr_enable, address 0xef [3] this register enables the contrast reduction feature and changes the meaning of the signal applied to the fb pin. 0 (default)the contrast reduction feature is disabled and the fast blank signal is interpreted as a bi-level signal. 1the contrast reduction feature is enabled and the fast blank signal is interpreted as a tri-level signal. contrast mode cntr_mode[1:0], address 0xf1 [3:2] the contrast level in the selected contrast reduction box is selected using the cntr_mode[1:0] bits. table 14. cntr_mode[1:0] function cntr_mode[1:0], description 00 (default) 25%. 01 50%. 10 75%. 11 100%. fast blank and contrast reduction programmable thresholds fb_level[1:0], address 0xf1 [5:4] controls the reference level for the fast blank comparator. cntr_level[1:0], address 0xf1 [7:6] controls the reference level for the contrast reduction comparator. the internal fast-blank and contrast-reduction signals are resolved from the tri-level fb signal using two comparators, as shown in figure 11. to facilitate compliance with different input level standards, the reference level to these comparators is programmable under the control of fb_level[1:0] and cntr_level[1:0]. the resulting thresholds are given in table 15. ? + programmable thresholds ? + contrast reduction comparator c fast blank comparator fast blank fb pin cntr enable cntr_level<1:0> fb_level<1:0> 05479-011 figure 11. fast blank and contrast reduction programmable threshold
ADV7184 rev. 0 | page 18 of 108 table 15. fast blank and contrast reduction programmable threshold i 2 c controls cntr_enable fb_level[1:0] cntr_level[1:0] fast bl anking threshold contrast reduction threshold 0 00 (default) xx 1.4 v n/a 0 01 xx 1.6 v n/a 0 10 xx 1.8 v n/a 0 11 xx 2.0 v n/a 1 00 (default) 00 1.6 v 0.4 v 1 01 01 1.8 v 0.6 v 1 10 10 2.0 v 0.8 v 1 11 11 2.2 v 2.0 v table 16. fb_status functions fb_status [3:0] bit name description 0 fb_status.0 fb_rise. a high value indicates there has been a rising edge on fb since the last i 2 c read. value is cleared by current i 2 c read (self-clearing bit). 1 fb_status.1 fb_fall. a high value indicates there has been a falling edge on fb since the last i 2 c read. value is cleared by current i 2 c read (self-clearing bit). 2 fb_status.2 fb_stat . value of fb input pin at time of read. 3 fb_status.3 fb_high. a high value indicates there has been a rising edge on fb since the last i 2 c read. value is cleared by current i 2 c read (self-clearing bit). fb_inv, address 0xed [3] (write only) the interpretation of the polarity of the signal applied to the fb pin can be changed using fb_inv. 0 (default)the fast blank pin is active high. 1the fast blank pin is active low. readback of fb pin status fb_status[3:0], address 0xed [7:4] fb_status[3:0] is a readback value that provides the system information on the status of the fb pins as shown in table 16. fb timing fb_sp_adjust[3:0], address 0xef [7:4] the critical information extracted from the fb signal is the time at which it switches relative to the input video. due to small timing inequalities either on the ic or on the pcb, it may be necessary to adjust the result by fractions of one clock cycle. this is controlled by fb_sp_adjust[3:0]. each lsb of fb_sp_adjust[3:0] corresponds to 1/8 of an adc clock cycle. increasing the value is equivalent to adding delay to the fb signal. the reset value is chosen to give equalized channels when the ADV7184 internal antialiasing filters are enabled and there is no unintentional delay on the pcb. the default value of fb_sp_adjust[3:0] is 0100. alignment of fb signal fb_delay[3:0], address 0xf0 [3:0] in the event of misalignment between the fb input signal and the other input signals (cvbs, rgb) or unequalized delays in their processing, it is possible to alter the delay of the fb signal in 28.63636 mhz clock cycles. (for a finer granularity delay of the fb signal, refer to fb_sp_adjust[3:0], address 0xef [7:4] above.) the default value of fb_delay[3:0] is 0100. color space converter manual adjust fb_csc_man, address 0xee [7] as shown in figure 9, the data from the cvbs source and the rgb source are both converted to ypbpr before being combined. in the case of the rgb source, the color space converter (csc) must be used to perform this conversion. when scart support is enabled, the parameters for the csc are automatically configured correctly for this operation. if the user wishes to use a different conversion matrix, this autoconfiguration can be disabled and the csc can be programmed manually. for details on this manual config- uration, please contact adi. 0 (default)the csc is configured automatically for the rgb to yprpb conversion. 1the csc can be configured manually (not recommended).
ADV7184 rev. 0 | page 19 of 108 global control registers register control bits listed in this section affect the whole chip. power-save modes power-down pdbp, address 0x0f [2] the digital core of the ADV7184 can be shut down by using a pin ( pwrdn ) and the pwrdn bit. the pdbp register controls which of the two has the higher priority. the default is to give the pin ( pwrdn ) priority. this allows the user to have the ADV7184 powered down by default. 0 (default)the digital core power is controlled by the pwrdn pin (the bit is disregarded). 1the bit has priority (the pin is disregarded). pwrdn, address 0x0f [5] setting the pwrdn bit switches the ADV7184 into a chip-wide power-down mode. the power-down stops the clock from entering the digital section of the chip, thereby freezing its operation. no i 2 c bits are lost during power-down. the pwrdn bit also affects the analog blocks and switches them into low current modes. the i 2 c interface itself is unaffected, and remains operational in power-down mode. the ADV7184 leaves the power-down state if the pwrdn bit is set to 0 (via i 2 c), or if the overall part is reset using the reset pin. note that pdbp must be set to 1 for the pwrdn bit to power down the ADV7184. 0 (default)the chip is operational. 1the ADV7184 is in chip-wide power-down. adc power-down control the ADV7184 contains four 10-bit adcs (adc 0, adc 1, adc 2, and adc3). if required, it is possible to power down each adc individually. ? in cvbs mode, adc 1 and adc 2 should be powered down to save on power consumption. ? in s-video mode, adc 2 should be powered down to save on power consumption. pwrdn_adc_0, address 0x3a [3] 0 (default)the adc is in normal operation. 1adc0 is powered down. pwrdn_adc_1, address 0x3a [2] 0 (default)the adc is in normal operation. 1adc1 is powered down. pwrdn_adc_2, address 0x3a [1] 0 (default)the adc is in normal operation. 1adc2 is powered down. pwrdn_adc_3, address 0x3a [0] 0 (default)the adc is in normal operation. 1adc3 is powered down. fb_pwrdn, address 0x0f [1] to achieve very low power-down current, it is necessary to prevent activity on toggling input pins from reaching circuitry that could consume current. fb_pwrdn gates signals from the fb input pin. 0 (default)the fb input is in normal operation. 1the fb input is in power-save mode. reset control res chip reset, address 0x0f [7] setting this bit, equivalent to controlling the reset pin on the ADV7184, issues a full chip reset. all i 2 c registers are reset to their default values, making these bits self-clearing. (some register bits do not have a reset value specified. they keep their last written value. those bits are marked as having a reset value of x in the register tables.) after the reset sequence, the part immediately starts to acquire the incoming video signal. executing a software reset takes approximately 2 ms. however, it is recommended to wait 5 ms before performing any more i 2 c writes. the i 2 c master controller receives a no acknowledge condition on the ninth clock cycle when chip reset is implemented. see the mpu port description section for a full description. 0 (default)operation is normal. 1the reset sequence starts. global pin control three-state output drivers tod, address 0x03 [6] this bit allows the user to three-state the output drivers of the ADV7184. upon setting the tod bit, the p15 to p0, hs, vs, field, and sfl pins are three-stated. the ADV7184 also supports three-stating via a dedicated pin, oe . the output drivers are three-stated if the tod bit or the oe pin is set high. the timing pins (hs/vs/field) can be forced active via the tim_oe bit. for more information on three-state control, refer to the three-state llc driver and the timing signals output enable sections. individual drive strength controls are provided via the dr_str_xx bits. 0 (default)the output drivers are enabled. 1the output drivers are three-stated.
ADV7184 rev. 0 | page 20 of 108 three-state llc driver tri_llc, address 0x1d [7] this bit allows the output drivers for the llc1 and llc2 pins of the ADV7184 to be three-stated. for more information on three-state control, refer to the three-state output drivers and the timing signals output enable sections. individual drive strength controls are provided via the dr_str_xx bits. 0 (default)the llc pin drivers work according to the dr_str_c[1:0] setting (pin enabled). 1the llc pin drivers are three-stated. timing signals output enable tim_oe, address 0x04 [3] the tim_oe bit should be regarded as an addition to the tod bit. setting it high forces the output drivers for hs, vs, and field into the active (that is, driving) state even if the tod bit is set. if set to low, the hs, vs, and field pins are three-stated, dependent on the tod bit. this functionality is useful if the decoder is to be used as a timing generator only. this may be the case if only the timing signals are to be extracted from an incoming signal, or if the part is in free-run mode where, for example, a separate chip can output a company logo. for more information on three-state control, refer to the three-state output drivers and the three-state llc driver sections. individual drive strength controls are provided via the dr_str_xx bits. 0 (default)hs, vs, and field are three-stated according to the tod bit. 1hs, vs, and field are forced active all the time. drive strength selection (data) dr_str[1:0], address 0xf4 [5:4] for emc and crosstalk reasons, it may be desirable to strengthen or weaken the drive strength of the output drivers. the dr_str[1:0] bits affect the p[15:0] output drivers. for more information on three-state control, refer to the drive strength selection (clock) and the drive strength selection (sync) sections. table 17. dr_str function dr_str[1:0] description 01 (default) medium low drive strength (2). 10 medium high drive strength (3). 11 high drive strength (4). drive strength selection (clock) dr_str_c[1:0] address 0xf4 [3:2] the dr_str_c[1:0] bits can be used to select the strength of the clock signal output driver (llc pin). for more information, refer to the drive strength selection (sync) and the drive strength selection (data) sections. table 18. dr_str_c function dr_str_c[1:0] description 01 (default) medium low drive strength (2). 10 medium high drive strength (3). 11 high drive strength (4). drive strength selection (sync) dr_str_s[1:0], address 0xf4 [1:0] the dr_str_s[1:0] bits allow the user to select the strength of the synchronization signals with which hs, vs, and f are driven. for more information, refer to the drive strength selection (clock) and the drive strength selection (data) sections. table 19. dr_str_s function dr_str_s[1:0] description 01 (default) medium low drive strength (2). 10 medium high drive strength (3). 11 high drive strength (4). enable subcarrier frequency lock pin en_sfl_pin, address 0x04 [1] the en_sfl_pin bit enables the output of subcarrier lock information (also known as genlock) from the ADV7184 to an encoder in a decoder-encoder back-to-back arrangement. 0 (default)the subcarrier frequency lock output is disabled. 1the subcarrier frequency lock information is presented on the sfl pin. polarity llc pin pclk, address 0x37 [0] the polarity of the clock that leaves the ADV7184 via the llc1 and llc2 pins can be inverted using the pclk bit. changing the polarity of the llc clock output may be necessary to meet the setup-and-hold time expectations of follow-on chips. this bit also inverts the polarity of the llc2 clock. 0the llc output polarity is inverted. 1 (default)the llc output polarity is normal (as per the timing diagrams).
ADV7184 rev. 0 | page 21 of 108 global status registers three registers provide summary information about the video decoder. the status_1, status_2, and status_3 registers contain status bits that report operational information to the user. status_1[7:0], address 0x10 [7:0] this read-only register provides information about the internal status of the ADV7184. see cil[2:0] count into lock, address 0x51 [2:0] and col[2:0] count out of lock, address 0x51 [5:3] for information on the timing. depending on the setting of the fscle bit, the status_1[0] and status_1[1] bits are based solely on horizontal timing information or on the horizontal timing and lock status of the color subcarrier. see the fscle fsc lock enable, address 0x51 [7] section. status_2[7:0], address 0x12 [7:0] see table 22. status_3[7:0], address 0x13 [7:0] see table 23. ad_result[2:0] autodetection result, address 0x10 [6:4] these bits report back on the findings from the autodetection block. for more information on enabling the autodetection block, see the general setup section. for information on configuring it, see the autodetection of sd modes section. table 20. ad_result function ad_result[2:0] description 000 ntsm-mj. 001 ntsc-443. 010 pal-m. 011 pal-60. 100 pal-bghid. 101 secam. 110 pal-combination n. 111 secam 525. table 21. status_1 function status 1 [7:0] bit name description 0 in_lock in lock (right now). 1 lost_lock lost lock (since la st read of this register). 2 fsc_lock fsc locked (right now). 3 follow_pw agc follows peak white algorithm. 4 ad_result.0 result of autodetection. 5 ad_result.1 result of autodetection. 6 ad_result.2 result of autodetection. 7 col_kill color kill active. table 22. status_2 function status 2 [7:0] bit name description 0 mvcs det detected macrovision color striping. 1 mvcs t3 macrovision color striping protection. conforms to type 3 if high, and to type 2 if low. 2 mv_ps det detected macrovision pseudo sync pulses. 3 mv_agc det detected macrovision agc pulses. 4 ll_nstd line length is nonstandard. 5 fsc_nstd fsc frequency is nonstandard. 6 reserved 7 reserved table 23. status_3 function status 3 [7:0] bit name description 0 inst_hlock horizontal lock indicator (ins tantaneous). 1 gemd gemstar detect. 2 sd_op_50hz flags whether 50 hz or 60 hz is present at output. 3 cvbs indicates if a cvbs signal is detect ed in yc/cvbs autodetection configuration 4 free_run_act indicates if the ADV7184 is in free run mode. outputs a blue screen by default. see the def_val_auto_en default value automatic en able, address 0x0c [1] bit for details about disabling this function. 5 std_fld_len field length is correct for currently selected video standard. 6 interlaced interlaced video de tected (field sequence found). 7 pal_sw_lock reliable sequence of swinging bursts detected.
ADV7184 rev. 0 | page 22 of 108 standard definition processor (sdp) 05479-012 digitized cvbs digitized y (yc) video data output standard definition processor digitized cvbs digitized c (yc) macrovision detection vbi data recovery standard autodetection luma filter luma digital fine clamp gain control luma resample luma 2d comb sllc control chroma filter chroma demod f sc recovery chroma digital fine clamp gain control chroma resample chroma 2d comb sync extract line length predictor resample control av code insertion measurement block (= >1 2 c) video data processing block figure 12. block diagram of the standard definition processor a block diagram of the ADV7184s standard definition processor (sdp) is shown in figure 12. the sdp block can handle standard definition video in cvbs, yc, and yprpb formats. it can be divided into a luminance and a chrominance path. if the input video is of a composite type (cvbs), both processing paths are fed with the cvbs input. sd luma path the input signal is processed by the following blocks: ? digital fine clamp. this block uses a high precision algorithm to clamp the video signal. ? luma filter block. this block contains a luma decimation filter (yaa) with a fixed response, and some shaping filters (ysh) that have selectable responses. ? luma gain control. the automatic gain control (agc) can operate on a variety of different modes, including gain based on the depth of the horizontal sync pulse, peak white mode, and fixed manual gain. ? luma resample. to correct for line-length errors as well as dynamic line-length changes, the data is digitally resampled. ? luma 2d comb. the two-dimensional comb filter provides yc separation. ? av code insertion. at this point, the decoded luma (y) signal is merged with the retrieved chroma values. av codes (as per itu-r. bt-656) can be inserted. sd chroma path the input signal is processed by the following blocks: ? digital fine clamp. this block uses a high precision algorithm to clamp the video signal. ? chroma demodulation. this block uses a color subcarrier (fsc) recovery unit to regenerate the color subcarrier for any modulated chroma scheme. the demodulation block then performs an am demodulation for pal and ntsc, and an fm demodulation for secam. ? chroma filter block. this block contains a chroma decimation filter (caa) with a fixed response, and some shaping filters (csh) that have selectable responses. ? gain control. automatic gain control (agc) can operate on several different modes, including gain based on the color subcarriers amplitude, gain based on the depth of the horizontal sync pulse on the luma channel, or fixed manual gain. ? chroma resample. the chroma data is digitally resampled to keep it perfectly aligned with the luma data. the resampling is done to correct for static and dynamic line- length errors of the incoming video signal. ? chroma 2d comb. the two-dimensional, 5-line, superadaptive comb filter provides high quality yc separation in case the input signal is cvbs. ? av code insertion. at this point, the demodulated chroma (cr and cb) signal is merged with the retrieved luma values. av codes (as per itu-r. bt-656) can be inserted.
ADV7184 rev. 0 | page 23 of 108 sync processing the ADV7184 extracts syncs embedded in the video data stream. there is currently no support for external hs/vs inputs. the sync extraction has been optimized to support imperfect video sources, such as videocassette recorders with head switches. the actual algorithm used employs a coarse detection based on a threshold crossing, followed by a more detailed detection using an adaptive interpolation algorithm. the raw sync information is sent to a line-length measurement and prediction block. the output of this block is then used to drive the digital resampling section to ensure that the ADV7184 outputs 720 active pixels per line. the sync processing on the ADV7184 also includes the following specialized postprocessing blocks that filter and condition the raw sync information retrieved from the digitized analog video. ? vsync processor. this block provides extra filtering of the detected vsyncs to give improved vertical lock. ? hsync processor. the hsync processor is designed to filter incoming hsyncs that have been corrupted by noise, providing much improved performance for video signals with stable time base but poor snr. vbi data recovery the ADV7184 can retrieve the following information from the input video: ? wide-screen signaling (wss) ? copy generation management system (cgms) ? closed caption (cc) ? macrovision protection presence ? gemstar-compatible data slicing ? teletex t ? vitc/vps the ADV7184 is also capable of automatically detecting the incoming video standard with respect to ? color subcarrier frequency ? field rate ? line rate the sdp can configure itself to support pal-bghid, pal-m/n, pal-combination n, ntsc-m, ntsc-j, secam 50 hz/60 hz, ntsc-4.43, and pal-60. general setup video standard selection the vid_sel[3:0] register allows the user to force the digital core into a specific video standard. under normal circum- stances, this should not be necessary. the vid_sel[3:0] bits default to an autodetection mode that supports pal, ntsc, secam, and variants thereof. the autodetection of sd modes section describes the autodetection system. autodetection of sd modes to guide the autodetect system, individual enable bits are provided for each of the supported video standards. setting the relevant bit to 0 inhibits the standard from being automatically detected . instead, the system picks the closest of the remaining enabled standards. the results of the autodetection can be read back via the status registers. see the global status registers section for more information. vid_sel[3:0], address 0x00 [7:4] table 24. vid_sel function vid_sel[3:0] description 0000 (default) autodetect (pal-bghid) ntsc-j (without pedestal), secam. 0001 autodetect (pal-bghid) ntsc-m (with pedestal), secam. 0010 autodetect (pal-n) (pedestal) ntsc-j (without pedestal), secam. 0011 autodetect (pal-n) (pedestal) ntsc-m (with pedestal), secam. 0100 ntsc-j (1). 0101 ntsc-m (1). 0110 pal 60. 0111 ntsc-4.43 (1). 1000 pal-bghid. 1001 pal-n (= pal-bghid (with pedestal)). 1010 pal-m (without pedestal). 1011 pal-m. 1100 pal-combination n. 1101 pal-combination n (with pedestal). 1110 secam. 1111 secam (with pedestal). ad_sec525_en enable autodetection of secam 525 line video, address 0x07 [7] 0 (default)disables the autodetection of a 525-line system with a secam style, fm-modulated color component. 1enables autodetection. ad_secam_en enable autodetection of secam, address 0x07 [6] 0disables the autodetection of secam. 1 (default)enables autodetection.
ADV7184 rev. 0 | page 24 of 108 ad_n443_en enable autodetection of ntsc-443, address 0x07 [5] 0disables the autodetection of ntsc style systems with a 4.43 mhz color subcarrier. 1 (default)enables autodetection. ad_p60_en enable autodetection of pal-60, address 0x07 [4] 0disables the autodetection of pal systems with a 60 hz field rate. 1 (default)enables autodetection. ad_paln_en enable autodetection of pal-n, address 0x07 [3] 0disables the detection of the pal n standard. 1 (default)enables autodetection. ad_palm_en enable autodetection of pal-m, address 0x07 [2] 0disables the autodetection of pal m. 1 (default)enables autodetection. ad_ntsc_en enable autodetection of ntsc, address 0x07 [1] 0disables the autodetection of standard ntsc. 1 (default)enables autodetection. ad_pal_en enable autodetection of pal, address 0x07 [0] 0disables the autodetection of standard pal. 1 (default)enables autodetection. subcarrier frequency lock inversion the sfl_inv bit controls the behavior of the pal switch bit in the sfl (genlock telegram) data stream. it was implemented to solve some compatibility issues with video encoders. it solves two problems. first, the pal switch bit is only meaningful in pal. some encoders (including analog devices encoders) also look at the state of this bit in ntsc. second, there was a design change in analog devices encoders from adv717x to adv719x. the older versions used the sfl (genlock telegram) bit directly, while the later ones invert the bit prior to using it. the reason for this is that the inversion compensated for the 1-line delay of an sfl (genlock telegram) transmission. as a result, adv717x encoders need the pal switch bit in the sfl (genlock telegram) to be 1 for ntsc to work. also, the adv7190/adv7191/adv7194 encoders need the pal switch bit in the sfl to be 0 to work in ntsc. if the state of the pal switch bit is wrong, a 180 phase shift occurs. in a decoder/encoder back-to-back system in which sfl is used, this bit must be set up properly for the specific encoder used. sfl_inv address 0x41 [6] 0 (default)makes the part sfl-compatible with adv7190/ adv7191/adv7194 and adv73xx encoders. 1makes the part sfl-compatible with adv717x encoders. lock-related controls lock information is presented to the user through bits [1:0] of the status 1 register. see the status_1[7:0], address 0x10 [7:0] section. figure 13 outlines the signal flow and the controls available to influence the way the lock status information is generated. srls select raw lock signal, address 0x51 [6] using the srls bit, the user can choose between two sources for determining the lock status (per bits [1:0] in the status 1 register). the time_win signal is based on a line-to-line evaluation of the horizontal synchronization pulse of the incoming video. it reacts quite quickly. the free_run signal evaluates the properties of the incoming video over several fields, and takes vertical synchronization information into account. 0 (default)selects the free_run signal. 1selects the time_win signal. 05479-013 1 0 time_win free_run status 1 [0] select the raw lock signal srls filter the raw lock signal cil[2:0], col[2:0] take f sc lock into account fscle status 1 [1] f sc lock 1 0 counter into lock counter out of lock memory figure 13. lock-related signal path
ADV7184 rev. 0 | page 25 of 108 fscle fsc lock enable, address 0x51 [7] the fscle bit allows the user to choose whether the status of the color subcarrier loop is taken into account when the overall lock status is determined and presented via bits [1:0] in status_1. this bit must be set to 0 when operating in yprpb component mode to generate a reliable hlock status bit. 0 (default)makes the overall lock status dependent on the horizontal sync lock only. 1makes the overall lock status dependent on horizontal sync lock and fsc lock. vs_coast[1:0], address 0xf9 [3:2] these bits are used to set vs free-run (coast) frequency. table 25. vs_coast[1:0] function vs_coast [1:0] description 00 (default) auto coast modefollows vs frequency from last video input 01 forces 50 hz coast mode 10 forces 60 hz coast mode 11 reserved cil[2:0] count into lock, address 0x51 [2:0] cil[2:0] determines the number of consecutive lines for which the into-lock condition must be true before the system switches into the locked state, and reports this via status_1[1:0]. it counts the value in lines of video. table 26. cil function cil[2:0] description 000 1 001 2 010 5 011 10 100 (default) 100 101 500 110 1000 111 100000 col[2:0] count out of lock, address 0x51 [5:3] col[2:0] determines the number of consecutive lines for which the out of lock condition must be true before the system switches into unlocked state, and reports this via status_0[1:0]. it counts the value in lines of video. table 27. col function col[2:0] description 000 1 001 2 010 5 011 10 100 (default) 100 101 500 110 1000 111 100000 st_noise_vld, hs tip noise measurement valid, address 0xde [3] (read only) 0the st_noise[10:0] measurement is not valid 1 (default)the st_noise[10:0] measurement is valid. st_noise[10:0] hs tip noise measurement, address 0xde [2:0], 0xdf [7:0] the st_noise[10:0] measures, over four fields, a readback value of the average of the noise in the hsync tip. st_noise_vld must be 1 for this measurement to be valid. 1 bit of st_noise[10:0] = 1 adc code. 1 bit of st_noise[10:0] = 1.6 v/4096 = 390.625 v. color controls these registers allow the user to control the picture appearance, including control of the active data in the event of video being lost. these controls are independent of any other controls. for instance, brightness control is independent of picture clamping, although both controls affect the signals dc level. con[7:0] contrast adjust, address 0x08 [7:0] this register allows the user to adjust the contrast of the picture. table 28. con function con[7:0] description 0x80 (default) gain on luma channel = 1 0x00 gain on luma channel = 0 0xff gain on luma channel = 2 sd_sat_cb[7:0] sd saturation cb channel, address 0xe3 [7:0] this register allows the user to control the gain of the cb channel only. the user can adjust the saturation of the picture. table 29. sd_sat_cb function sd_sat_cb[7:0] description 0x80 (default) gain on cb channel = 1 0x00 gain on cb channel = 0 0xff gain on cb channel = 2 sd_sat_cr[7:0] sd saturation cr channel, address 0xe4 [7:0] this register allows the user to control the gain of the cr channel only. the user can adjust the saturation of the picture. table 30. sd_sat_cr function sd_sat_cr[7:0] description 0x80 (default) gain on cr channel = 1 0x00 gain on cr channel = 0 0xff gain on cr channel = 2
ADV7184 rev. 0 | page 26 of 108 sd_off_cb[7:0] sd offset cb channel, address 0xe1 [7:0] this register allows the user to select an offset for data on the cb channel only and adjust the hue of the picture. there is a functional overlap with the hue [7:0] register. table 31.sd_off_cb function sd_off_cb[7:0] description 0x80 (default) 0 mv offset applied to the cb channel 0x00 ?568 mv offset appl ied to the cb channel 0xff +568 mv offset appl ied to the cb channel sd_off_cr [7:0] sd offset cr channel, address 0xe2 [7:0] this register allows the user to select an offset for data on the cr channel only and adjust the hue of the picture. there is a functional overlap with the hue [7:0] register. table 32. sd_off_cr function sd_off_cr[7:0] description 0x80 (default) 0 mv offset applied to the cr channel 0x00 ?568 mv offset applied to the cr channel 0xff +568 mv offset applied to the cr channel bri[7:0] brightness adjust, address 0x0a [7:0] this register controls the brightness of the video signal. it allows the user to adjust the brightness of the picture. table 33. bri function bri[7:0] description 0x00 (default) offset of the luma channel = 0 mv 0x7f offset of the luma channel = +204 mv 0x80 offset of the luma channel = ?204 mv hue[7:0] hue adjust, address 0x0b [7:0] this register contains the value for the color hue adjustment. it allows the user to adjust the hue of the picture. hue[7:0] has a range of 90, with 0x00 equivalent to an adjustment of 0. the resolution of hue[7:0] is 1 bit = 0.7. the hue adjustment value is fed into the am color demodulation block. therefore, it only applies to video signals that contain chroma information in the form of an am modulated carrier (cvbs or y/c in pal or ntsc). it does not affect secam and does not work on component video inputs (yprpb). table 34. hue function hue[7:0] description 0x00 (default) phase of th e chroma signal = 0 0x7f phase of the chroma signal = +90 0x80 phase of the chroma signal = ?90 def_y[5:0] default value y, address 0x0c [7:2] if the ADV7184 loses lock on the incoming video signal or if there is no input signal, the def_y[5:0] bits allow the user to specify a default luma value to be output. the register is used under the following conditions: ? if def_val_auto_en bit is set to high and the ADV7184 loses lock to the input video signal. this is the intended mode of operation (automatic mode). ? the def_val_en bit is set, regardless of the lock status of the video decoder. this is a forced mode that may be useful during configuration. the def_y[5:0] values define the 6 msbs of the output video. the remaining lsbs are padded with 0s. for example, in 8-bit mode, the output is y[7:0] = {def_y[5:0], 0, 0}. the value for y is set by the def_y[5:0] bits. a value of 0x0d produces a blue color in conjunction with the def_c[7:0] default setting. register 0x0c has a default value of 0x36. def_c[7:0] default value c, address 0x0d [7:0] the def_c[7:0] register complements the def_y[5:0] value. it defines the 4 msbs of cr and cb values to be output if ? the def_val_auto_en bit is set to high and the ADV7184 cant lock to the input video (automatic mode). ? def_val_en bit is set to high (forced output). the data that is finally output from the ADV7184 for the chroma side is cr[7:0] = {def_c[7:4], 0, 0, 0, 0}, cb[7:0] = {def_c[3:0], 0, 0, 0, 0}. the values for cr and cb are set by def_c[7:0] bits. a value of 0x7c produces a blue color in conjunction with the def_y[5:0] default setting. def_val_en default value enable, address 0x0c [0] this bit forces the use of the default values for y, cr, and cb. refer to the descriptions for def_y and def_c for additional information. in this mode, the decoder also outputs a stable 27 mhz clock, hs, and vs. 0 (default)outputs a colored screen determined by user- programmable y, cr, and cb values when the decoder free- runs. free-run mode is turned on and off by the def_val_auto_en bit. 1forces a colored screen output determined by user- programmable y, cr, and cb values. this overrides picture data even if the decoder is locked.
ADV7184 rev. 0 | page 27 of 108 def_val_auto_en default value automatic enable, address 0x0c [1] this bit enables the automatic use of the default values for y, cr, and cb when the ADV7184 cannot lock to the video signal. 0disables free-run mode. if the decoder is unlocked, it outputs noise. 1 (default)enables free-run mode. a colored screen set by the user-programmable y, cr, and cb values is displayed when the decoder loses lock. clamp operation the input video is ac-coupled into the ADV7184 through a 0.1 f capacitor. it is recommended that the range of the input video signal is 0.5 v to 1.6 v (typically 1 v p-p). if the signal exceeds this range, it cannot be processed correctly in the decoder. since the input signal is ac-coupled into the decoder, its dc value needs to be restored. this process is referred to as clamping the video. this section explains the general process of clamping on the ADV7184, and shows the different ways in which a user can configure its behavior. the ADV7184 uses a combination of current sources and a digital processing block for clamping, as shown in figure 14. the analog processing channel shown is replicated three times inside the ic. while only one single channel (and only one adc) is needed for a cvbs signal, two independent channels are needed for yc (s-vhs) type signals, and three independent channels are needed to allow component signals (yprpb) to be processed. the clamping can be divided into two sections: ? clamping before the adc (analog domain): current sources. ? clamping after the adc (digital domain): digital processing block. the adcs can digitize an input si gnal only if it resides within their 1.6 v input voltage range. an input signal with a dc level that is too large or too small is clipped at the top or bottom of the adc range. the primary task of the analog clamping circuits is to ensure that the video signal stays within the valid adc input window so that the analog-to-digital conversion can take place. it is not necessary to clamp the input signal with a very high accuracy in the analog domain as long as the video signal fits the adc range. after digitization, the digital fine clamp block corrects for any remaining variations in dc level. since the dc level of an input video signal refers directly to the brightness of the picture transmitted, it is important to perform a fine clamp with high accuracy; otherwise, brightness variations may occur. further- more, dynamic changes in the dc level almost certainly lead to visually objectionable artifacts, and must therefore be prohibited. the clamping scheme must be able to acquire a newly connected video signal with a completely unknown dc level, and it must maintain the dc level during normal operation. to quickly acquire an unknown video signal, the large current clamps may be activated. it is assumed that the amplitude of the video signal at this point is of a nominal value. control of the coarse and fine current clamp parameters is automatically performed by the decoder. standard definition video signals may have excessive noise on them. in particular, cvbs signals transmitted by terrestrial broadcast and demodulated using a tuner usually show very large levels of noise (>100 mv). a voltage clamp would be unsuitable for this type of video signal. instead, the ADV7184 uses a set of four current sources that can cause coarse (>0.5 ma) and fine (<0.1 ma) currents to flow into and away from the high impedance node that carries the video signal (see figure 14). the following sections describe the i 2 c signals that can be used to influence the behavior of the clamps on the ADV7184. cclen current clamp enable, address 0x14 [4] the current clamp enable bit allows the user to switch off the current sources in the analog front end altogether. this may be useful if the incoming analog video signal is clamped externally. 0the current sources are switched off. 1 (default)the current sources are enabled. 05479-014 coarse current sources fine current sources data pre- processor (dpp) adc sdp with digital fine clamp clamp control a nalo g video input figure 14. clamping overview
ADV7184 rev. 0 | page 28 of 108 dct[1:0] digital clamp timing, address 0x15 [6:5] the clamp timing register determines the time constant of the digital fine clamp circuitry. it is important to realize that the digital fine clamp reacts very quickly since it is supposed to immediately correct any residual dc level error for the active line. the time constant of the digital fine clamp must be much quicker than the one from the analog blocks. by default, the time constant of the digital fine clamp is adjusted dynamically to suit the currently connected input signal. table 35. dct function dct[1:0] description 00 slow (tc = 1 sec). 01 medium (tc = 0.5 sec). 10 (default) fast (tc = 0.1 sec). 11 determined by the ADV7184, depending on the i/p video parameters. dcfe digital clamp freeze enable, address 0x15 [4] this register bit allows the user to freeze the digital clamp loop at any time. it is intended for users who would like to do their own clamping. users should disable the current sources for analog clamping via the appropriate register bits, wait until the digital clamp loop settles, and then freeze it via the dcfe bit. 0 (default)the digital clamp is operational. 1the digital clamp loop is frozen. luma filter data from the digital fine clamp block is processed by three sets of filters. the data format at this point is cvbs for cvbs input or luma only for y/c and yprpb input formats. ? luma antialias filter (yaa). the ADV7184 receives video at a rate of 27 mhz. for 4 oversampled video, the adcs sample at 54 mhz, and the first decimation is performed inside the dpp filters. therefore, the data rate into the sdp core is always 27 mhz. the itu-r bt.601 recommends a sampling frequency of 13.5 mhz. the luma antialias filter decimates the oversampled video using a high quality, linear phase, low-pass filter that preserves the luma signal while at the same time attenuating out-of-band components. the luma antialias filter has a fixed response. ? luma shaping filters (ysh). the shaping filter block is a programmable low-pass filter with a wide variety of responses. it can be used to selectively reduce the luma video signal bandwidth (needed prior to scaling, for example). for some video sources that contain high frequency noise, reducing the bandwidth of the luma signal improves visual picture quality. a follow-on video compression stage may work more efficiently if the video is low-pass filtered. the ADV7184 has two responses for the shaping filter: one that is used for good quality cvbs, component, and s-vhs type sources, and a second for nonstandard cvbs signals. the ysh filter responses also include a set of notches for pal and ntsc. however, it is recommended to use the comb filters for yc separation. ? digital resampling filter. this block is used to allow dynamic resampling of the video signal to alter parameters such as the time base of a line of video. fundamentally, the resampler is a set of low-pass filters. the actual response is chosen by the system with no requirement for user intervention. figure 16 through figure 19 show the overall response of all filters together. unless otherwise noted, the filters are set into a typical wideband mode. y-shaping filter for input signals in cvbs format, the luma shaping filters play an essential role in removing the chroma component from a composite signal. yc separation must aim for best possible crosstalk reduction while still retaining as much bandwidth (especially on the luma component) as possible. high quality yc separation can be achieved by using the internal comb filters of the ADV7184. comb filtering, however, relies on the frequency relationship of the luma component (multiples of the video line rate) and the color subcarrier (fsc). for good quality cvbs signals, this relationship is known; the comb filter algorithms can be used to separate out luma and chroma with high accuracy. for nonstandard video signals, the frequency relationship may be disturbed and the comb filters may not be able to remove all crosstalk artifacts in an optimum fashion without the assistance of the shaping filter block. an automatic mode is provided. here, the ADV7184 evaluates the quality of the incoming video signal and selects the filter responses in accordance with the signal quality and video standard. yfsm, wysfmovr, and wysfm allow the user to manually override the automatic decisions in part or in full. the luma shaping filter has three control registers ? ysfm[4:0] allows the user to manually select a shaping filter mode (applied to all video signals) or to enable an automatic selection (dependent on video quality and video standard). ? wysfmovr allows the user to manually override the wysfm decision. ? wysfm[4:0] allows the user to select a different shaping filter mode for good quality cvbs, component (yprpb), and s-vhs (yc) input signals.
ADV7184 rev. 0 | page 29 of 108 05479-015 auto select luma shaping filter to complement comb set ysfm ysfm in auto mode? 00000 or 00001 video quality bad good select wideband filter as per wysfm[4:0] select automatic wideband filter wysfmovr 1 0 use ysfm selected filter regardless for good and bad video yes no figure 15. ysfm and wysfm control flowchart in automatic mode, the system preserves the maximum possible bandwidth for good cvbs sources (since they can successfully be combed) as well as for luma components of yprpb and yc sources, since they need not be combed. for poor quality signals, the system selects from a set of proprietary shaping filter responses that complements comb filter operation in order to reduce visual artifacts. the decisions of the control logic are shown in figure 15. ysfm[4:0] y shaping filter mode, address 0x17 [4:0] the y shaping filter mode bits allow the user to select from a wide range of low-pass and notch filters. when switched in automatic mode, the filter is selected based on other register selections, such as detected video standard, as well as properties extracted from the incoming video itself, such as quality and time base stability. the automatic selection always picks the widest possible bandwidth for the video input encountered. if the ysfm settings specify a filter (that is, ysfm is set to values other than 00000 or 00001), the chosen filter is applied to all video, regardless of its quality. in automatic selection mode, the notch filters are used only for bad quality video signals. for all other video signals, wideband filters are used; see table 36. wysfmovr wideband y shaping filter override, address 0x18,[7] setting the wysfmovr bit enables use of the wysfm[4:0] settings for good quality video signals. for more information, refer to the general discussion of the luma shaping filters in the y-shaping filter section and the flowchart shown in figure 15. 0the shaping filter for good quality video signals is selected automatically. 1 (default)enables manual override via wysfm[4:0]. table 36. ysfm function ysfm[4:0] description 00000 automatic selection including a wide notch response (pal/ntsc/secam) 00001 (default) automatic selection including a narrow notch response (pal/ntsc/secam) 00010 svhs 1 00011 svhs 2 00100 svhs 3 00101 svhs 4 00110 svhs 5 00111 svhs 6 01000 svhs 7 01001 svhs 8 01010 svhs 9 01011 svhs 10 01100 svhs 11 01101 svhs 12 01110 svhs 13 01111 svhs 14 10000 svhs 15 10001 svhs 16 10010 svhs 17 10011 svhs 18 (ccir 601) 10100 pal nn 1 10101 pal nn 2 10110 pal nn 3 10111 pal wn 1 11000 pal wn 2 11001 ntsc nn 1 11010 ntsc nn 2 11011 ntsc nn 3 11100 ntsc wn 1 11101 ntsc wn 2 11110 ntsc wn 3 11111 reserved
ADV7184 rev. 0 | page 30 of 108 wysfm[4:0] wide band y shaping filter mode, address 0x18 [4:0] the wysfm[4:0] bits allow the user to manually select a shaping filter for good quality video signals, for example, cvbs with stable time base, luma component of yprpb, and luma component of yc. the wysfm bits are only active if the wysfmovr bit is set to 1. see the general discussion of the shaping filter settings in the y-shaping filter section. table 37. wysfm function wysfm[4:0] description 00000 do not use 00001 do not use 00010 svhs 1 00011 svhs 2 00100 svhs 3 00101 svhs 4 00110 svhs 5 00111 svhs 6 01000 svhs 7 01001 svhs 8 01010 svhs 9 01011 svhs 10 01100 svhs 11 01101 svhs 12 01110 svhs 13 01111 svhs 14 10000 svhs 15 10001 svhs 16 10010 svhs 17 10011 (default) svhs 18 (ccir 601) 10100C11111 do not use the filter plots in figure 16 show the s-vhs 1 (narrowest) to s-vhs 18 (widest) shaping filter settings. figure 18 shows the pal notch filter responses. the ntsc-compatible notches are shown in figure 19. 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 010 8 6 4 212 05479-016 frequency (mhz) combined y antialias, s-vhs low-pass filters, y resample amplitude (db) figure 16. y s-vhs combined responses 0 ?20 ?40 ?60 ?80 ?100 ?120 010 8 6 4 212 05479-017 frequency (mhz) amplitude (db) combined y antialias, ccir mode shaping filter, y resample figure 17. y s-vhs 18 extra wideband filter (ccir 601-compliant) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 010 8 6 4 212 05479-018 frequency (mhz) combined y antialias, pal notch filters, y resample amplitude (db) figure 18. y pal notch filter responses 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 010 8 6 4 212 05479019 frequency (mhz) combined y antialias, ntsc notch filters, y resample amplitude (db) figure 19. ntsc notch filter responses
ADV7184 rev. 0 | page 31 of 108 chroma filter data from the digital fine clamp block is processed by three sets of filters. the data format at this point is cvbs for cvbs inputs, chroma only for y/c, or cr/cb interleaved for yprpb input formats. ? chroma antialias filter (caa). the ADV7184 over- samples the cvbs by a factor of 2 and the chroma/crcb by a factor of 4. a decimating filter (caa) is used to preserve the active video band and to remove any out-of- band components. the caa filter has a fixed response. ? chroma shaping filters (csh). the shaping filter block (csh) can be programmed to perform a variety of low- pass responses. it can be used to selectively reduce the bandwidth of the chroma signal for scaling or compression. ? digital resampling filter. this block is used to allow dynamic resampling of the video signal to alter parameters such as the time base of a line of video. fundamentally, the resampler is a set of low-pass filters. the actual response is chosen by the system without user intervention. the plots in figure 20 show the overall response of all filters together, from sh1 (narrowest) to sh5 (widest) in addition to the wideband mode (in red). 0 ?10 ?20 ?30 ?40 ?50 ?60 05 4 3 2 16 05479-020 frequency (mhz) combined c antialias, c shaping filter, c resampler attenuation (db) figure 20. chroma shaping filter responses csfm[2:0] c-shaping filter mode, address 0x17 [7] the c-shaping filter mode bits allow the user to select from a range of low-pass filters for the chrominance signal. table 38. csfm function csfm[2:0] description 000 (default) 1.5 mhz bandwidth filter. 001 2.17 mhz bandwidth filter. 010 sh1. 011 sh2. 100 sh3. 101 sh4. 110 sh5. 111 wideband mode. gain operation the gain control within the ADV7184 is done on a purely digital basis. the input adcs support a 10-bit range, mapped into a 1.6 v analog voltage range. gain correction takes place after the digitization in the form of a digital multiplier. advantages of this architecture over the commonly used pga (programmable gain amplifier) before the adcs include that the gain is now completely independent of supply, temperature, and process variations. as shown in figure 21, the ADV7184 can decode a video signal as long as it fits into the adc window. the two components to this are the amplitude of the input signal and the dc level on which it resides. the dc level is set by the clamping circuitry (see the clamp operation section). if the amplitude of the analog video signal is too high, clipping may occur, resulting in visual artifacts. the analog input range of the adc, together with the clamp level, determines the maximum supported amplitude of the video signal. the minimum supported amplitude of the input video is determined by the ADV7184s ability to retrieve horizontal and vertical timing and to lock to the color burst if present. there are separate gain control units for luma and chroma data. both can operate independently of each other. the chroma unit, however, can also take its gain value from the luma path. the possible agc modes are summarized in table 39. it is possible to freeze the automatic gain control loops. this causes the loops to stop updating and the agc-determined gain at the time of the freeze to stay active until the loop is either unfrozen or the gain mode of operation is changed. the currently active gain from any of the modes can be read back. refer to the description of the dual function manual gain registers, lg[11:0] luma gain and cg[11:0] chroma gain, in the luma gain and chroma gain sections.
ADV7184 rev. 0 | page 32 of 108 05479-021 analog voltage range supported by adc (1.6v range for ADV7184) data pre- processor (dpp) adc sdp (gain selection only) maximum voltage minimum voltage clamp level gain control figure 21. gain control overview table 39. agc modes input video type luma gain chroma gain any manual gain luma. manual gain chroma. dependent on color burst amplitude. dependent on horizontal sync depth. taken from luma path. dependent on color burst amplitude. cvbs peak white. taken from luma path. dependent on color burst amplitude. dependent on horizontal sync depth. taken from luma path. dependent on color burst amplitude. y/c peak white. taken from luma path. yprpb dependent on horizontal sync depth. taken from luma path. luma gain lagc[2:0] luma automatic gain control, address 0x2c [6:4] the luma automatic gain control mode bits select the mode of operation for the gain control in the luma path. there are adi internal parameters to customize the peak white gain control. contact adi for more information. table 40. lagc function lagc[2:0] description 000 manual fixed gain (use lmg[11:0]). 001 agc (blank level to sync tip). peak white algorithm off. 010 (default) agc (blank level to sync tip). peak white algorithm on. 011 reserved. 100 reserved. 101 reserved. 110 reserved. 111 freeze gain. lagt[1:0] luma automatic gain timing, address 0x2f [7:6] the luma automatic gain timing register allows the user to influence the tracking speed of the luminance automatic gain control. note that this register only has an effect if the lagc[2:0] register is set to 001, 010, 011, or 100 (automatic gain control modes). if peak white agc is enabled and active (see the section status_1[7:0], address 0x10 [7:0]), the actual gain update speed is dictated by the peak white agc loop and, as a result, the lagt settings have no effect. as soon as the part leaves peak white agc, lagt becomes relevant again. the update speed for the peak white algorithm can be custom- ized by the use of internal parameters. contact adi for more information. table 41. lagt function lagt[1:0] description 00 slow (tc = 2 sec). 01 medium (tc = 1 sec). 10 fast (tc = 0.2 sec). 11 (default) adaptive. lg[11:0] luma gain, address 0x2f [3:0]; address 0x30 [7:0]; lmg[11:0] luma manual gain, address 0x2f [3:0]; address 0x30 [7:0] luma gain [11:0] is a dual-function register. if written to, a desired manual luma gain can be programmed. this gain becomes active if the lagc[2:0] mode is switched to manual fixed gain. equation 2 and equation 3 show how to calculate a desired gain for ntsc and pal, respectively. ntsc luma_gain = 1128 4095 ] 0 : 11 [ 1024 < = 0.90783.63 (2) pal luma_gain = 1222 4095 ] 0 : 11 [ 1024 < = 0.8383.351 (3)
ADV7184 rev. 0 | page 33 of 108 if read back, this register returns the current gain value. depending on the setting in the lagc[2:0] bits, this is one of the following values: ? luma manual gain value (lagc[2:0] set to luma manual gain mode). ? luma automatic gain value (lagc[2:0] set to any of the automatic modes). table 42. lg/lmg function lg[11:0]/lmg[11:0] read/write description lmg[11:0] = x write manual gain for luma path. lg[11:0] read actually used gain. for example, to program the ADV7184 into manual fixed gain mode with a desired gain of 0.95 for the ntsc standard: 1. use equation 2 to convert the gain: 0.95 1128 = 1071.6 2. truncate to integer value: 1071.6 = 1071 3. convert to hexadecimal: 1071d = 0x42f 4. split into two registers and program: luma gain control 1 [3:0] = 0x4 luma gain control 2 [7:0] = 0x2f 5. enable manual fixed gain mode: set lagc[2:0] to 000 betacam enable betacam levels, address 0x01 [5] if yprpb data is routed through the ADV7184, the automatic gain control modes can target different video input levels, as outlined in table 45. note that the betacam bit is valid only if the input mode is yprpb (component). the betacam bit sets the target value for agc operation. a review of the following sections is useful: ? insel[3:0] input selection, address 0x00 [3:0] to find how component video (yprpb) can be routed through the ADV7184. ? video standard selection to select the various standards, for example, with and without pedestal. the automatic gain control (agc) algorithms adjust the levels based on the setting of the betacam bit (see table 43). table 43. betacam function betacam description 0 (default) assuming yprpb is selected as input format. selecting pal with pedestal selects mii. selecting pal without pedestal selects smpte. selecting ntsc with pedestal selects mii. selecting ntsc without pedestal selects smpte. 1 assuming yprpb is selected as input format. selecting pal with pedestal selects betacam. selecting pal without pedestal selects betacam variant. selecting ntsc with pedestal selects betacam. selecting ntsc without pedestal selects betacam variant. pw_upd peak white update, address 0x2b [0] the peak white and average video algorithms determine the gain based on measurements taken from the active video. the pw_upd bit determines the rate of gain change. lagc[2:0] must be set to the appropriate mode to enable the peak white or average video mode in the first place. for more information, refer to the lagc[2:0] luma automatic gain control, address 0x2c [6:4] section. 0updates the gain once per video line. 1 (default)updates the gain once per field. chroma gain cagc[1:0] chroma automatic gain control, address 0x2c [1:0] these two bits select the basic mode of operation for automatic gain control in the chroma path. table 44. cagc function cagc[1:0] description 00 manual fixed gain (use cmg[11:0]). 01 use luma gain for chroma. 10 (default) automatic gain (based on color burst). 11 freeze chroma gain. table 45. betacam levels name betacam (mv) betacam variant (mv) smpte (mv) mii (mv) y range 0 to 714 (incl. 7.5% pedestal) 0 to 714 0 to 700 0 to 700 (incl. 7.5% pedestal) pb and pr range C467 to +467 C505 to +505 C350 to +350 C324 to +324 sync depth 286 286 300 300
ADV7184 rev. 0 | page 34 of 108 cagt[1:0] chroma automatic gain timing, address 0x2d [7:6] this register allows the user to influence the tracking speed of the chroma automatic gain control. it has an effect only if the cagc[1:0] register is set to 10 (automatic gain). table 46. cagt function cagt[1:0] description 00 slow (tc = 2 sec). 01 medium (tc = 1 sec). 10 fast (tc = 0.2 sec). 11 (default) adaptive. cg[11:0] chroma gain, address 0x2d [3:0]; address 0x2e [7:0] cmg[11:0] chroma manual gain, address 0x2d [3:0]; address 0x2e [7:0] cg[11:0] is a dual-function register. if written to, a desired manual chroma gain can be programmed. this gain becomes active if the cagc[1:0] mode is switched to manual fixed gain. refer to equation 4 for calculating a desired gain. if read back the register returns the current gain value. depending on the setting in the cagc[1:0] bits, this is either: ? chroma manual gain value (cagc[1:0] set to chroma manual gain mode). ? chroma automatic gain value (cagc[1:0] set to any of the automatic modes). table 47. cg/cmg function cg[11:0]/cmg[11:0] read/write description cmg[11:0] write manual gain for chroma path. cg[11:0] read currently active gain. () 4 ... 0 1024 4095 0 _ = < = cg gain chroma (4) for example, freezing the automatic gain loop and reading back the cg[11:0] register results in a value of 0x47a. 1. convert the readback value to decimal: 0x47a = 1146d 2. apply equation 4 to convert the readback value: 1146/1024 = 1.12 cke color kill enable, address 0x2b [6] this bit allows the optional color kill function to be switched on or off. for qam-based video standards (pal and ntsc) and fm-based systems (secam), the threshold for the color kill decision is selectable via the ckillthr[2:0] bits. if color kill is enabled, and if the color carrier of the incoming video signal is less than the threshold for 128 consecutive video lines, color processing is switched off (black and white output). to switch the color processing back on, another 128 consecutive lines with a color burst greater than the threshold are required. the color kill option only works for input signals with a modu- lated chroma part. for component input (yprpb), there is no color kill. 0disables color kill. 1 (default)enables color kill. ckillthr[2:0] color kill threshold, address 0x3d [6:4] the ckillthr[2:0] bits allow the user to select a threshold for the color kill function. the threshold applies only to qam- based (ntsc and pal) or fm-modulated (secam) video standards. to enable the color kill function, the cke bit must be set. for settings 000, 001, 010, and 011, chroma demodulation inside the ADV7184 may not work satisfactorily for poor input video signals. table 48. ckillthr function description ckillthr[2:0] secam ntsc, pal 000 no color kill kill at < 0.5% 001 kill at < 5% kill at < 1.5% 010 kill at < 7% kill at < 2.5% 011 kill at < 8% kill at < 4.0% 100 (default) kill at < 9.5% kill at < 8.5% 101 kill at < 15% kill at < 16.0% 110 kill at < 32% kill at < 32.0% 111 reserved for adi internal use only. do not select. chroma transient improvement (cti) the signal bandwidth allocated for chroma is typically much smaller than that of luminance. in the past, this was a valid way to fit a color video signal into a given overall bandwidth because the human eye is less sensitive to chrominance than to luminance. the uneven bandwidth, however, may lead to visual artifacts in sharp color transitions. at the border of two bars of color, both components (luma and chroma) change at the same time (see figure 22). due to the higher bandwidth, the signal transition of the luma component is usually much sharper than that of the chroma component. the color edge is not sharp but blurred, in the worst case over several pixels.
ADV7184 rev. 0 | page 35 of 108 054790-22 luma signal demodulated chroma signal luma signal with a transition, accompanied by a chroma transition original, "slow" chroma transition prior to cti sharpened chroma transition at the output of cti figure 22. cti luma/chroma transition the cti block examines the input video data. it detects transitions of chroma, and can be programmed to steepen the chroma edges in an attempt to artificially restore lost color bandwidth. however, it operates only on edges above a certain threshold to ensure that noise is not emphasized. care has also been taken to avoid edge ringing and undesirable saturation and hue distortion. chroma transient improvements are needed primarily for signals that experienced severe chroma bandwidth limitations. for those types of signals, it is strongly recommended to enable the cti block via cti_en. cti_en chroma transient improvement enable, address 0x4d [0] 0disables the cti block. 1 (default)enables the cti block. cti_ab_en chroma transient improvement alpha blend enable, address 0x4d [1] this bit enables an alpha-blend function, which mixes the transient improved chroma with the original signal. the sharpness of the alpha blending can be configured via the cti_ab[1:0] bits. for the alpha blender to be active, the cti block must be enabled via the cti_en bit. 0disables the cti alpha blender. 1 (default)enables the cti alpha blender. cti_ab[1:0] chroma transient improvement alpha blend, address 0x4d [3:2] this controls the behavior of alpha-blend circuitry that mixes the sharpened chroma signal with the original one. it thereby controls the visual impact of cti on the output data. for cti_ab[1:0] to become active, the cti block must be enabled via the cti_en bit, and the alpha blender must be switched on via cti_ab_en. sharp blending maximizes the effect of cti on the picture, but may also increase the visual impact of small amplitude, high frequency chroma noise. table 49. cti_ab function cti_ab[1:0] description 00 sharpest mixing between sharpened and original chroma signal 01 sharp mixing 10 smooth mixing 11 (default) smoothest alpha blend function cti_c_th[7:0] cti chroma threshold, address 0x4e [7:0] the cti_c_th[7:0] value is an unsigned, 8-bit number speci- fying how big the amplitude step in a chroma transition has to be in order to be steepened by the cti block. programming a small value into this register causes even smaller edges to be steepened by the cti block. making cti_c_th[7:0] a large value causes the block to improve large transitions only. the default value for cti_c_th[7:0] is 0x08, indicating the threshold for the chroma edges prior to cti. digital noise reduction (dnr), and luma peaking filter dnr is based on the assumption that high frequency signals with low amplitude are probably noise and therefore that their removal improves picture quality. there are two dnr blocks in the ADV7184: the dnr1 block before the luma peaking filter and the dnr2 block after the luma peaking filter, as shown in figure 23. luma outpu t dnr1 luma peaking filter dnr2 luma signal 05479-023 figure 23. dnr and peaking block diagram dnr_en digital noise reduction enable, address 0x4d [5] 0bypasses dnr (disables it). 1 (default) enables dnr on the luma data. dnr_th[7:0] dnr noise threshold, address 0x50 [7:0] the dnr1 block is positioned before the luma peaking block. the dnr_th[7:0] value is an unsigned 8-bit number, which determines the maximum edge that is interpreted as noise and therefore blanked from the luma data. programming a large value into dnr_th[7:0] causes the dnr block to interpret even large transients as noise and remove them. as a result, the effect on the video data is more visible. programming a small value causes only small transients to be seen as noise and to be removed. the recommended dnr_th[7:0] setting for a/v inputs is 0x04, and the recommended dnr_th[7:0] setting for tuner inputs is 0x0a.
ADV7184 rev. 0 | page 36 of 108 the default value for dnr_th[7:0] is 0x08, indicating the threshold for maximum luma edges to be interpreted as noise. peaking_gain[7:0], luma peak ing gain, address 0xfb [7:0] this filter can be manually enabled. the user can boost or attenuate the midregion of the y spectrum around 3 mhz. the peaking filter can visually improve the picture by showing more definition on the picture details that contain frequency components around 3 mhz. the default value (0x40) in this register passes through the luma data unaltered (0 db response). a lower value attenuates the signal and a higher value amplifies it. a plot of the filters responses is shown in figure 24. 15 ?20 07 05479-024 frequency (mhz) filter response (db) 10 5 0 ?5 ?10 ?15 123456 peaking gain using bp filter figure 24. peaking filter responses dnr_th2[7:0] dnr noise threshold 2, address 0xfc [7:0] the dnr2 block is positioned after the luma peaking block, so it affects the amplified luma signal. it operates in the same way as the dnr1 block but has an independent threshold control, dnr_th2[7:0]. this value is an unsigned 8-bit number, which determines the maximum edge that is still interpreted as noise and, therefore, blanked from the luma data. programming a large value into dnr_th2[7:0] causes the dnr block to interpret even large transients as noise and remove them. as a result, the effect on the video data is more visible. programming a small value causes only small transients to be seen as noise and removed. comb filters the comb filters of the ADV7184 have been greatly improved to automatically handle video of all types, standards, and levels of quality. the ntsc and pal configuration registers allow the user to customize comb filter operation, depending on which video standard is detected (by autodetection) or selected (by manual programming). in addition to the bits listed in this section, there are some other adi internal controls; contact adi for more information. ntsc comb filter settings used for ntsc-m/j cvbs inputs. nsfsel[1:0] split filter selection ntsc, address 0x19 [3:2] nsfsel[1:0] selects how much of the overall signal bandwidth is fed to the combs. a narrow bandwidth split filter gives better performance on diagonal lines, but leaves more dot crawl in the final output image. the opposite is true for a wide bandwidth split filter. table 50.nsfsel function nsfsel[1:0] description 00 (default) narrow 01 medium 10 medium 11 wide ctapsn[1:0] chroma comb taps ntsc, address 0x38 [7:6] table 51. ctapsn function ctapsn[1:0] description 00 do not use 01 ntsc chroma comb adapts 3 lines (3 taps) to 2 lines (2 taps) 10 (default) ntsc chroma comb adapts 5 lines (5 taps) to 3 lines (3 taps) 11 ntsc chroma comb adapts 5 lines (5 taps) to 4 lines (4 taps) ccmn[2:0] chroma comb mode ntsc, address 0x38 [5:3] see table 52. ycmn[2:0] luma comb mode ntsc, address 0x38 [2:0] see table 53.
ADV7184 rev. 0 | page 37 of 108 table 52. ccmn function ccmn[2:0] description configuration adaptive 3-line chroma comb for ctapsn = 01 adaptive 4-line chroma comb for ctapsn = 10 000 (default) adaptive comb mode adaptive 5-line chroma comb for ctapsn = 11 100 disable chroma comb fixed 2-line chroma comb for ctapsn = 01 fixed 3-line chroma comb for ctapsn = 10 101 fixed chroma comb (top lines of line memory) fixed 4-line chroma comb for ctapsn = 11 fixed 3-line chroma comb for ctapsn = 01 fixed 4-line chroma comb for ctapsn = 10 110 fixed chroma comb (all lines of line memory) fixed 5-line chroma comb for ctapsn = 11 fixed 2-line chroma comb for ctapsn = 01 fixed 3-line chroma comb for ctapsn = 10 111 fixed chroma comb (bottom lines of line memory) fixed 4-line chroma comb for ctapsn = 11 table 53.ycmn function ycmn[2:0] description configuration 000 (default) adaptive comb mode adap tive 3-line (3 taps) luma comb 100 disable luma comb use lo w-pass/notch filter; see the y-shaping filter section 101 fixed luma comb (top lines of line memory) fixed 2-line (2 taps) luma comb 110 fixed luma comb (all lines of line me mory) fixed 3-line (3 taps) luma comb 111 fixed luma comb (bottom lines of line memory) fixed 2-line (2 taps) luma comb pal comb filter settings used for pal-b/g/h/i/d, pal-m, pal-combinational n, pal-60 and ntsc-443 cvbs inputs. psfsel[1:0] split filter selection pal, address 0x19 [1:0] psfsel[1:0] selects how much of the overall signal bandwidth is fed to the combs. a wide bandwidth split filter eliminates dot crawl, but shows imperfections on diagonal lines. the opposite is true for a narrow bandwidth split filter. table 54. psfsel function psfsel[1:0] description 00 narrow 01 (default) medium 10 wide 11 widest ctapsp[1:0] chroma comb taps pal, address 0x39 [7:6] table 55. ctapsp function ctapsp[1:0] description 00 do not use. 01 pal chroma comb adapts 5 lines (3 taps) to 3 lines (2 taps); cancels cross luma only. 10 pal chroma comb adapts 5 lines (5 taps) to 3 lines (3 taps); cancels cross luma and hue error less well. 11 (default) pal chroma comb adapts 5 li nes (5 taps) to 4 lines (4 taps); cancels cross luma and hue error well. ccmp[2:0] chroma comb mode pal, address 0x39 [5:3] see table 56. ycmp[2:0] luma comb mode pal, address 0x39 [2:0] see table 57. vertical blank control each vertical blank control register has the same meaning for the following bits: 00early by 1 line. 10delay by 1 line. 11delay by 2 lines. 01 (default) is described under each register. nvbiolcm[1:0] ntsc vbi odd field luma comb mode, address 0xeb [7:6] these bits control the first combed line after vbi on ntsc odd field (luma comb). 01 (default)smpte170-compliant, blank lines 1C20, 264C282, comb half lines. nvbielcm[1:0] ntsc vbi even field luma comb mode, address 0xeb [5:4] these bits control the first combed line after vbi on ntsc even field (luma comb). 01 (default)smpte170-compliant, blank lines 1C20, 264C282, comb half lines.
ADV7184 rev. 0 | page 38 of 108 pvbiolcm[1:0] pal vbi odd field luma comb mode, address 0xeb [3:2] these bits control the first combed line after vbi on pal odd field (luma comb). 01 (default)bt470-compliant, blank lines 624C22, 311C335, comb half lines. pvbielcm[1:0] pal vbi even field luma comb mode, address 0xeb [1:0] these bits control the first combed line after vbi on pal even field (luma comb). 01 (default)bt470-compliant, blank lines 624C22, 311C335, comb half lines. nvbioccm[1:0] ntsc vbi odd field chroma comb mode, address 0xec [7:6] these bits control the first combed line after vbi on ntsc odd field (chroma comb). 01 (default)smpte170-compliant, no color on lines 1C20, 264C282, chroma present on half lines. nvbieccm[1:0] ntsc vbi even field chroma comb mode, address 0xec [5:4] these bits control the first combed line after vbi on ntsc even field (chroma comb). 01 (default)smpte170-compliant, no color on lines 1C20, 264C282, chroma present on half lines. pvbioccm[1:0] pal vbi odd field chroma comb mode, address 0xec [3:2] these bits control the first combed line after vbi on pal odd field (chroma comb). 01 (default)bt470-compliant, no color on lines 624C22, 311C335, chroma present on half lines. pvbieccm[1:0] pal vbi even field chroma comb mode, address 0xec [1:0] these bits control the first combed line after vbi on pal even field (chroma comb). 01 (default)bt470-compliant, no color on lines 624C22, 311C335, chroma present on half lines. table 56. ccmp function ccmp[2:0] description configuration adaptive 3-line chroma comb for ctapsp = 01 adaptive 4-line chroma comb for ctapsp = 10 000 (default) adaptive comb mode adaptive 5-line chroma comb for ctapsp = 11 100 disable chroma comb. fixed 2-line chroma comb for ctapsp = 01 fixed 3-line chroma comb for ctapsp = 10 101 fixed chroma comb (top lines of line memory) fixed 4-line chroma comb for ctapsp = 11 fixed 3-line chroma comb for ctapsp = 01 fixed 4-line chroma comb for ctapsp = 10 110 fixed chroma comb (all lines of line memory) fixed 5-line chroma comb for ctapsp = 11 fixed 2-line chroma comb for ctapsp = 01 fixed 3-line chroma comb for ctapsp = 10 111 fixed chroma comb (bottom lines of line memory) fixed 4-line chroma comb for ctapsp = 11 table 57. ycmp function ycmp[2:0] description configuration 000 (default) adaptive comb mode adap tive 5 lines (3 taps) luma comb 100 disable luma comb use lo w-pass/notch filter; see the y-shaping filter section 101 fixed luma comb (top lines of line memory) fixed 3 lines (2 taps) luma comb 110 fixed luma comb (all lines of line me mory) fixed 5 lines (3 taps) luma comb 111 fixed luma comb (bottom lines of line memory) fixed 3 lines (2 taps) luma comb
ADV7184 rev. 0 | page 39 of 108 av code insertion and controls this section describes the i 2 c-based controls that affect ? insertion of av codes into the data stream ? data blanking during the vertical blank interval (vbi) ? the range of data values permitted in the output data stream ? the relative delay of luma vs. chroma signals note that some of the decoded vbi data is being inserted during the horizontal blanking interval. see the gemstar data recovery section for more information. bt656-4 itu standard bt-r.656-4 enable, address 0x04 [7] the itu has changed the position for toggling the v bit within the sav eav codes for ntsc between revisions 3 and 4. the bt656-4 standard bit allows the user to select an output mode that is compliant with either the previous or the new standard. for more information, review the standard at http://www.itu.int. note that the standard change affects ntsc only and has no bearing on pal. 0 (default)the bt656-3 specification is used. the v bit goes low at eav of lines 10 and 273. 1the bt656-4 specification is used. the v bit goes low at eav of lines 20 and 283. sd_dup_av duplicate av codes, address 0x03 [0] depending on the output interface width, it may be necessary to duplicate the av codes from the luma path into the chroma path. in an 8-bit-wide output interface (cb/y/cr/y interleaved data), the av codes are defined as ff/00/00/av, with av being the transmitted word that contains information about h/v/f. in this output interface mode, the following assignment takes place: cb = ff, y = 00, cr = 00, and y = av. in a 16-bit output interface where y and cr/cb are delivered via separate data buses, the av code is over the whole 16 bits. the sd_dup_av bit allows the user to replicate the av codes on both buses, so the full av sequence can be found on the y bus and on the cr/cb bus. see figure 25. 0 (default)the av codes are in single fashion (to suit 8-bit interleaved data output). 1the av codes are duplicated (for 16-bit interfaces). vbi_en vertical blanking interval data enable, address 0x03 [7] the vbi enable bit allows data such as intercast and closed caption data to be passed through the luma channel of the decoder with a minimal amount of filtering. all data for line 1 to line 21 is passed through and available at the output port. the ADV7184 does not blank the luma data, and automatically switches all filters along the luma data path into their widest bandwidth. for active video, the filter settings for ysh and ypk are restored. refer to the bl_c_vbi blank chroma during vbi, address 0x04 [2] section for information on the chroma path. 0 (default)all video lines are filtered/scaled. 1only the active video region is filtered/scaled. bl_c_vbi blank chroma during vbi, address 0x04 [2] when bl_c_vbi is set high, the cr and cb values of all vbi lines are blanked. this is done so any data that may arrive during vbi is not decoded as color and output through cr and cb. as a result, it is possible to send vbi lines into the decoder, then output them through an encoder again, undistorted. without this blanking, any wrongly decoded color is encoded by the video encoder; therefore, the vbi lines are distorted. 0decodes and outputs color during vbi. 1 (default)blanks cr and cb values during vbi. 05479-025 y data bus 00 av y ff 00 00 av y ff cr/cb data bu s 00 00 av cb ff 00 cb av code section av code section ff 00 00 av cb av code section cb/y/cr/y interleaved 8-bit interface 16-bit interface 16-bit interface sd_dup_av = 1 sd_dup_av = 0 figure 25. av code duplication control
ADV7184 rev. 0 | page 40 of 108 range range selection, address 0x04 [0] av codes (as per itu-r bt-656, formerly known as ccir-656) consist of a fixed header made up of 0xff and 0x00 values. these two values are reserved and therefore not to be used for active video. additionally, the itu specifies that the nominal range for video should be restricted to values between 16 and 235 for luma and 16 to 240 for chroma. the range bit allows the user to limit the range of values output by the ADV7184 to the recommended value range. in any case, it ensures that the reserved values of 255d (0xff) and 00d (0x00) are not presented on the output pins unless they are part of an av code header. table 58. range function range description 0 16 y 235 16 c 240 1 (default) 1 y 254 1 c 254 auto_pdc_en automatic programmed delay control, address 0x27 [6] enabling the auto_pdc_en function activates a function within the ADV7184 that automatically programs lta[1:0] and cta[2:0] to have the chroma and luma data match delays for all modes of operation. 0the adv7183 uses the lta[1:0] and cta[2:0] values for delaying luma and chroma samples. refer to the lta[1:0] luma timing adjust, address 0x27 [1:0] and the cta[2:0] chroma timing adjust, address 0x27 [5:3] sections. 1 (default)the ADV7184 automatically programs the lta and cta values to have luma and chroma aligned at the output. manual registers lta[1:0] and cta[2:0] are not used. lta[1:0] luma timing adjust, address 0x27 [1:0] this register allows the user to specify a timing difference between chroma and luma samples. note that there is a certain functionality overlap with the cta[2:0] register. for manual programming, use the following defaults: ? cvbs input lta[1:0] = 00 ? yc input lta[1:0] = 01 ? yprpb input lta[1:0] =01 table 59. lta function lta[1:0] description 00 (default) no delay 01 luma 1 clk (37 ns) delayed 10 luma 2 clk (74 ns) early 11 luma 1 clk (37 ns) early cta[2:0] chroma timing adjust, address 0x27 [5:3] this register allows the user to specify a timing difference between chroma and luma samples. this may be used to compensate for external filter group delay differences in the luma vs. chroma path, and to allow a different number of pipeline delays while processing the video downstream. review this functionality together with the lta[1:0] register. the chroma can only be delayed/advanced in chroma pixel steps. one chroma pixel step is equal to two luma pixels. the programmable delay occurs after demodulation, where one can no longer delay by luma pixel steps. for manual programming, use the following defaults: ? cvbs input cta[2:0] = 011 ? yc input cta[2:0] = 101 ? yprpb input cta[2:0] =110 table 60. cta function cta[2:0] description 000 not used 001 chroma + 2 chroma pixel (early) 010 chroma + 1 chroma pixel (early) 011 (default) no delay 100 chroma C 1 chroma pixel (late) 101 chroma C 2 chroma pixel (late) 110 chroma C 3 chroma pixel (late) 111 not used synchronization output signals hs configuration the following controls allow the user to configure the behavior of the hs output pin only: ? beginning of hs signal via hsb[10:0] ? end of hs signal via hse[10:0] ? polarity of hs using phs the hs begin and hs end registers allow the user to freely position the hs output (pin) within the video line. the values in hsb[10:0] and hse[10:0] are measured in pixel units from the falling edge of hs. using both values, the user can program both the position and length of the hs output signal. hsb[10:0] hs begin, address 0x34 [6:4], address 0x35 [7:0] the position of this edge is controlled by placing a binary number into hsb[10:0]. the number applied offsets the edge with respect to an internal counter that is reset to 0 immediately after eav code ff, 00, 00, xy (see figure 26). hsb[10:0] is set to 00000000010, which is 2 llc1 clock cycles from count[0]. the default value of hsb[10:0] is 0x002, indicating that the hs pulse starts two pixels after the falling edge of hs.
ADV7184 rev. 0 | page 41 of 108 table 61. hs timing parameters characteristic standard hs begin adjust (hsb[10:0]) (default) hs end adjust (hse[10:0]) (default) hs to active video (llc1 clock cycles) (c in figure 26) (default) active video samples/line (d in figure 26) total llc1 clock cycles (e in figure 26) ntsc 00000000010 00000000000 272 720y + 720c = 1440 1716 ntsc square pixel 00000000010 00000000000 276 640y + 640c = 1280 1560 pal 00000000010 00000000000 284 720y + 720c = 1440 1728 05479-026 e active video llc1 pixel bus hs cr y ff 00 00 xy 80 10 80 10 80 10 ff 00 00 xy cb y cr y cb y cr 4 llc1 d hsb[10:0] hse[10:0] c e d sav active video h blank eav figure 26. hs timing hse[10:0] hs end, address 0x34 [2:0]; address 0x36 [7:0] the position of this edge is controlled by placing a binary number into hse[10:0]. the number applied offsets the edge with respect to an internal counter that is reset to 0 immediately after eav code ff, 00, 00, xy (see figure 26). hse is set to 00000000000, which is 0 llc1 clock cycles from count[0]. the default value of hse[10:0] is 000, indicating that the hs pulse ends 0 pixels after falling edge of hs. for example: 1. to shift the hs toward active video by 20 llc1s, add 20 llc1s to both hsb and hse, that is, hsb[10:0] = [00000010110], hse[10:0] = [00000010100]. 2. to shift the hs away from active video by 20 llc1s, add 1696 llc1s to both hsb and hse (for ntsc), that is, hsb[10:0] = [11010100010], hse[10:0] = [11010100000]. 1696 is derived from the ntsc total number of pixels = 1716. to move 20 llc1s away from active video is equal to subtracting 20 from 1716 and adding the result in binary to both hsb[10:0] and hse[10:0]. phs polarity hs, address 0x37 [7] the polarity of the hs pin can be inverted using the phs bit. 0 (default)hs is active high. 1hs is active low. vs and field configuration the following controls allow the user to configure the behavior of the vs and field output pins, as well as to generate embedded av codes: ? adv encoder-compatible signals via newavmode ? pvs, pf ? hvstim ? vsbho, vsbhe ? vseho, vsehe ? for ntsc control: o nvbegdelo, nvbegdele, nvbegsign, nvbeg[4:0] o nvenddelo, nvenddele, nvendsign, nvend[4:0] o nftogdelo, nftogdele, nftogsign, nftog[4:0] ? for pal control: o pvbegdelo, pvbegdele, pvbegsign, pvbeg[4:0] o pvenddelo, pvenddele, pvendsign, pvend[4:0] o pftogdelo, pftogdele, pftogsign, pftog[4:0]
ADV7184 rev. 0 | page 42 of 108 newavmode new av mode, address 0x31 [4] 0eav/sav codes are generated to suit adi encoders. no adjustments are possible. 1 (default)enables the manual position of the vsync, field, and av codes using register 0x34 to register 0x37 and register 0xe5 to register 0xea. default register settings are ccir656- compliant; see figure 27 for ntsc and figure 32 for pal. for recommended manual user settings, see table 62 and figure 28 for ntsc; see table 63 and figure 33 for pal. table 62. recommended user settings for ntsc (see figure 28) register register name write 0x31 vsync field control 1 0x1a 0x32 vsync field control 2 0x81 0x33 vsync field control 3 0x84 0x34 hsync position 1 0x00 0x35 hsync position 2 0x00 0x36 hsync position 3 0x7d 0x37 polarity 0xa1 0xe5 ntsv_v_bit_beg 0x41 0xe6 ntsc_v_bit_end 0x84 0xe7 ntsc_f_bit_tog 0x06 hvstim horizontal vs timing, address 0x31 [3] the hvstim bit allows the user to select where the vs signal is being asserted within a line of video. some interface circuitry may require vs to go low while hs is low. 0 (default)the start of the line is relative to hse. 1the start of the line is relative to hsb. vsbho vs begin horizontal position odd, address 0x32 [7] this bit selects the position within a line at which the vs pin (not the bit in the av code) becomes active. some follow-on chips require the vs pin to change state only when hs is high/low. 0 (default)the vs pin goes high at the middle of a line of video (odd field). 1the vs pin changes state at the start of a line (odd field). vsbhe vs begin horizontal position even, address 0x32 [6] this bit selects the position within a line at which the vs pin (not the bit in the av code) becomes active. some follow-on chips require the vs pin to change state when only hs is high/low. 0the vs pin goes high at the middle of a line of video (even field). 1 (default)the vs pin changes state at the start of a line (even field). vseho vs end horizontal position odd, address 0x33 [7] this bit selects the position within a line at which the vs pin (not the bit in the av code) becomes inactive. some follow-on chips require the vs pin to change state only when hs is high/low. 0the vs pin goes low (inactive) at the middle of a line of video (odd field). 1 (default)the vs pin changes state at the start of a line (odd field). vsehe vs end horizontal position even, address 0x33 [6] this bit selects the position within a line at which the vs pin (not the bit in the av code) becomes inactive. some follow-on chips require the vs pin to change state only when hs is high/low. 0 (default)the vs pin goes low (inactive) at the middle of a line of video (even field). 1the vs pin changes state at the start of a line (even field). pvs polarity vs, address 0x37 [5] the polarity of the vs pin can be inverted using the pvs bit. 0 (default)vs is active high. 1vs is active low. pf polarity field, address 0x37 [3] the polarity of the field pin can be inverted using the pf bit. 0 (default)field is active high. 1field is active low.
ADV7184 rev. 0 | page 43 of 108 05479-027 output video field 1 field 2 h v f output video h v f 525 1 2 3 4 5 6 7 8 9 10 11 12 13 19 20 21 22 nvbeg[4:0] = 0x5 nvbeg[4:0] = 0x5 nvend[4:0] = 0x4 nvend[4:0] = 0x4 nftog[4:0] = 0x3 nftog[4:0] = 0x3 *bt.656-4 reg 0x04, bit 7 = 1 *bt.656-4 reg 0x04, bit 7 = 1 *applies if nemavmode = 0: must be manually shifted if newavmode = 1. 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 283 284 285 figure 27. ntsc default (bt.656). the polarity of h, v, and f is embedded in the data. nvbeg[4:0] =0x0 nvend[4:0] = 0x3 05479-028 field 1 output video field output hs output nftog[4:0] = 0x5 vs output 525 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 21 22 field 2 output video field output hs output vs output 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 284 285 nvbeg[4:0] = 0x0 nvend[4:0] = 0x3 nftog[4:0] = 0x5 figure 28. ntsc typical vsync/field positions using register writes in table 62
ADV7184 rev. 0 | page 44 of 108 05479-029 advance begin of vsync by nvbeg[4:0] delay begin of vsync by nvbeg[4:0] vsync begin nvbegsign odd field? 0 1 no yes nvbegdelo vsbho additional delay by 1 line advance by 0.5 line 1 0 1 0 nvbegdele vsbhe additional delay by 1 line advance by 0.5 line 1 0 1 0 not valid for user programming figure 29. ntsc vsync begin nvbegdelo ntsc vsync begin delay on odd field, address 0xe5 [7] 0 (default)no delay. 1delays vsync going high on an odd field by a line relative to nvbeg. nvbegdele ntsc vsync begin delay on even field, address 0xe5 [6] 0 (default)no delay. 1delays vsync going high on an even field by a line relative to nvbeg. nvbegsign ntsc vsync begin sign, address 0xe5 [5] 0delays the start of vsync. set for user manual programming. 1 (default)advances the start of vsync. not recommended for user programming. nvbeg[4:0] ntsc vsync begin, address 0xe5 [4:0] the default value of nvbeg is 00101, indicating the ntsc vsync begin position. for all ntsc/pal vsync timing controls, both the v bit in the av code and the vsync on the vs pin are modified. 05479-030 advance end of vsync by nvend[4:0] delay end of vsync by nvend[4:0] vsync end nvendsign odd field? 0 1 no yes nvenddelo vseho additional delay by 1 line advance by 0.5 line 1 0 1 0 nvenddele vsehe additional delay by 1 line advance by 0.5 line 1 0 1 0 not valid for user programming figure 30. ntsc vsync end nvenddelo ntsc vsync end delay on odd field, address 0xe6 [7] 0 (default)no delay. 1delays vsync from going low on an odd field by a line relative to nvend. nvenddele ntsc vsync end delay on even field, address 0xe6 [6] 0 (default)no delay. 1delays vsync from going low on an even field by a line relative to nvend. nvendsign ntsc vsync end sign, address 0xe6 [5] 0 (default)delays the end of vsync. set for user manual programming. 1advances the end of vsync. not recommended for user programming. nvend[4:0] ntsc vsync end, address 0xe6 [4:0] the default value of nvend is 00100, indicating the ntsc vsync end position. for all ntsc/pal vsync timing controls, both the v bit in the av code and the vsync on the vs pin are modified.
ADV7184 rev. 0 | page 45 of 108 nftogdelo ntsc field toggle delay on odd field, address 0xe7 [7] 0 (default)no delay. 1delays the field toggle/transition on an odd field by a line relative to nftog. nftogdele ntsc field toggle delay on even field, address 0xe7 [6] 0no delay. 1 (default)delays the field toggle/transition on an even field by a line relative to nftog. 05479-031 advance toggle of field by nftog[4:0] delay toggle of field by nftog[4:0] nftogsign odd field? 0 1 no yes nftogdele additional delay by 1 line 1 0 nftogdelo additional delay by 1 line 1 0 field toggle not valid for user programming figure 31. ntsc field toggle nftogsign ntsc field toggle sign, address 0xe7 [5] 0delays the field transition. set for user manual programming. 1 (default)advances the field transition. not recommended for user programming. nftog[4:0] ntsc field toggle, address 0xe7 [4:0] the default value of nftog is 00011, indicating the ntsc field toggle position. for all ntsc/pal field timing controls, both the f bit in the av code and the field signal on the field/de pin are modified. pvbegdelo pal vsync begin delay on odd field, address 0xe8 [7] 0 (default)no delay. 1delays vsync going high on an odd field by a line relative to pvbeg. pvbegdele pal vsync begin delay on even field, address 0xe8 [6] 0 (default)no delay. 1 (default)delays vsync going high on an even field by a line relative to pvbeg. pvbegsign pal vsync begin sign, address 0xe8 [5] 0delays the beginning of vsync. set for user manual programming. 1 (default)advances the beginning of vsync. not recommended for user programming. pvbeg[4:0] pal vsync begin, address 0xe8 [4:0] the default value of pvbeg is 00101, indicating the pal vsync begin position. for all ntsc/pal vsync timing controls, both the v bit in the av code and the vsync on the vs pin are modified. table 63. recommended user settings for pal (see figure 33) register register name write 0x31 vsync field control 1 0x1a 0x32 vsync field control 2 0x81 0x33 vsync field control 3 0x84 0x34 hsync position 1 0x00 0x35 hsync position 2 0x00 0x36 hsync position 3 0x7d 0x37 polarity 0xa1 0xe8 pal_v_bit_beg 0x41 0xe9 pal_v_bit_end 0x84 0xea pal_f_bit_tog 0x06
ADV7184 rev. 0 | page 46 of 108 05479-032 field 1 output video h v f 622 623 624 625 1 2 3 4 5 6 7 8 9 10 22 23 24 pvbeg[4:0] = 0x5 pvend[4:0] = 0x4 pftog[4:0] = 0x3 field 2 output video h v f pvbeg[4:0] = 0x5 pvend[4:0] = 0x4 pftog[4:0] = 0x3 310 311 312 313 314 315 316 317 318 319 320 321 322 335 336 337 figure 32. pal default (bt.656). the polarity of h, v, and f is embedded in the data. 05479-033 field 1 622 623 624 625 123 45 678 91011 2324 310 311 312 313 314 315 316 317 318 319 320 321 322 323 336 337 pvbeg[4:0] = 0x1 pvend[4:0] = 0x4 pftog[4:0] = 0x6 field 2 output video field output hs output vs output output video field output hs output vs output pvbeg[4:0] = 0x1 pvend[4:0] = 0x4 pftog[4:0] = 0x6 figure 33. pal typical vsync/field positions using register writes in table 63
ADV7184 rev. 0 | page 47 of 108 05479-034 advance begin of vsync by pvbeg[4:0] delay begin of vsync by pvbeg[4:0] vsync begin pvbegsign odd field? 0 1 no yes pvbegdelo vsbho additional delay by 1 line advance by 0.5 line 1 0 1 0 pvbegdele vsbhe additional delay by 1 line advance by 0.5 line 1 0 1 0 not valid for user programming figure 34. pal vsync begin pvenddelo pal vsync end delay on odd field, address 0xe9 [7] 0 (default)no delay. 1delays vsync going low on an odd field by a line relative to pvend. pvenddele pal vsync end delay on even field, address 0xe9 [6] 0 (default)no delay. 1delays vsync going low on an even field by a line relative to pvend. pvendsign pal vsync end sign, address 0xe9 [5] 0 (default)delays the end of vsync. set for user manual programming. 1advances the end of vsync. not recommended for user programming. 05479-035 advance end of vsync by pvend[4:0] delay end of vsync by pvend[4:0] vsync end pvendsign odd field? 0 1 no yes pvenddelo vseho additional delay by 1 line advance by 0.5 line 1 0 1 0 pvenddele vsehe additional delay by 1 line advance by 0.5 line 1 0 1 0 not valid for user programming figure 35. pal vsync end pvend[4:0] pal vsync end, address 0xe9 [4:0] the default value of pvend is 10100, indicating the pal vsync end position. for all ntsc/pal vsync timing controls, both the v bit in the av code and the vsync on the vs pin are modified. pftogdelo pal field toggle delay on odd field, address 0xea [7] 0 (default)no delay. 1delays the f toggle/transition on an odd field by a line relative to pftog. pftogdele pal field toggle delay on even field, address 0xea [6] 0 (default)no delay. 1 (default)delays the f toggle/transition on an even field by a line relative to pftog.
ADV7184 rev. 0 | page 48 of 108 pftogsign pal field toggle sign, address 0xea [5] 0delays the field transition. set for user manual programming. 1 (default)advances the field transition. not recommended for user programming. pftog pal field toggle, address 0xea [4:0] the default value of pftog is 00011, indicating the pal field toggle position. for all ntsc/pal field timing controls, the f bit in the av code and the field signal on the field/de pin are modified. 05479-036 advance toggle of field by ptog[4:0] delay toggle of field by pftog[4:0] pftogsign odd field? 0 1 no yes pftogdele additional delay by 1 line 1 0 pftogdelo additional delay by 1 line 1 0 field toggle not valid for user programming figure 36. pal f toggle sync processing the ADV7184 has two additional sy nc processing blocks that postprocess the raw synchronization information extracted from the digitized input video. if desired, the blocks can be disabled via the following two i 2 c bits. enhspll enable hsync processor, address 0x01 [6] the hsync processor is designed to filter incoming hsyncs that have been corrupted by noise, providing improved per- formance for video signals with stable time bases but poor snr. 0disables the hsync processor. 1 (default)enables the hsync processor. envsproc enable vsync processor, address 0x01 [3] this block provides extra filtering of the detected vsyncs to give improved vertical lock. 0disables the vsync processor. 1 (default)enables the vsync processor. vbi data decode there are two vbi data slicers on the ADV7184. the first is called is called the vbi data processor (vdp) and the second is called vbi system 2. the vdp can slice both low bandwidth standards and high bandwidth standards such as teletext. vbi system 2 can slice low data-rate vbi standards only. the vdp is capable of slicing multiple vbi data standards on sd video. it decodes the vbi data on the incoming cvbs/yc or yuv data. the decoded results are available as ancillary data in output 656 data stream. for low data rate vbi standards like cc/wss/cgms the user can read the decoded data bytes from i 2 c registers. the vbi data standards that can be decoded by the vdp are: pa l teletext system a or c or d itu-bt-653 teletext system b/wst itu-bt-653 vps (video programming system) etsi en 300 231 v 1.3.1 vitc (vertical interval time codes) wss (wide screen signaling) bt.1119-1/ etsi.en.300294 ccap (closed captioning) ntsc teletext system b and d itu-bt-653 teletext system c/nabts itu-bt-653/eia-516 vitc (vertical interval time codes) cgms (copy generation management system) eia-j cpr-1204/iec 61880 gemstar ccap (closed captioning) eia-608 the vbi data standard that the vdp decodes on a particular line of incoming video has been set by default as described in table 64. this can be overridden manually and any vbi data can be decoded on any line. the details of manual program- ming are described in table 65 and table 66.
ADV7184 rev. 0 | page 49 of 108 vdp default configuration the vdp can decode different vbi data standards on a line-to- line basis. the various standards supported by default on different lines of vbi are explained in table 64. vdp manual configuration man_line_pgm enable manual line programming of vbi standards, address 0x64 [7] user sub map the user can configure the vdp to decode different standards on a line-to-line basis through manual line programming. for this, the user has to set the man_line_pgm bit. the user needs to write into all the line programming registers vbi_data_px_ny (register 0x64 to register 0x77, user sub map). 0 (default)the vdp decodes default standards on lines as shown in table 64. 1vbi standards to be decoded are manually programmed. vbi_data_px_ny [3:0] vbi standard to be decoded on line x for pal, line y for ntsc, address 0x64-0x77, user sub map these are related 4-bit clusters contained from register 0x64 to register 0x77 in the user sub map. the 4-bit, line pro- gramming registers, named vbi_data_px_ny, identifies the vbi data standard that would be decoded on line number x in pal or on line number y in ntsc mode. the different types of vbi standards decoded by vbi_data_px_ny are shown in table 65. note that the interpretation of its value depends on whether the ADV7184 is in pal or ntsc mode. table 64. default standards on lines for pal and ntsc pal C 625/50 ntsc C 525/60 line no. default vbi data decoded line no. default vbi data decoded line no. default vbi data decoded line no. default vbi data decoded 6 wst 318 vps 23 gemstar-1x C - 7 wst 319 wst 24 gemstar-1x 286 gemstar-1x 8 wst 320 wst 25 gemstar-1x 287 gemstar-1x 9 wst 321 wst C C 288 gemstar-1x 10 wst 322 wst C C C - 11 wst 323 wst C C C - 12 wst 324 wst 10 nabts 272 nabts 13 wst 325 wst 11 nabts 273 nabts 14 wst 326 wst 12 nabts 274 nabts 15 wst 327 wst 13 nabts 275 nabts 16 vps 328 wst 14 vitc 276 nabts 17 C 329 vps 15 nabts 277 vitc 18 C 330 C 16 vitc 278 nabts 19 vitc 331 C 17 nabts 279 vitc 20 wst 332 vitc 18 nabts 280 nabts 21 wst 333 wst 19 nabts 281 nabts 22 ccap 334 wst 20 cgms 282 nabts 23 wss 335 ccap 21 ccap 283 cgms 24 + full odd field wst 336 wst 22 + full odd field nabts 284 ccap 337 + full even field wst 285 + full even field nabts table 65. vbi data standardsmanual configuration vbi_data_px_ny 625/50 C pal 525/60 C ntsc 0000 disable vdp. disable vdp. 0001 teletext system identified by vdp_ttxt_type. teletext system identified by vdp_ttxt_type. 0010 vps C etsi en 300 231 v 1.3.1. reserved. 0011 vitc. vitc. 0100 wss bt.1119-1/etsi.en.300294. cgms eia-j cpr-1204/iec 61880. 0101 reserved. gemstar_1x. 0110 reserved. gemstar_2x. 0111 ccap. ccap eia-608. 1000 C 1111 reserved. reserved.
ADV7184 rev. 0 | page 50 of 108 table 66.vbi data standards to be decoded on line px (pal) or line ny (ntsc) address signal name register location dec hex vbi_data_p6_n23 vdp_line_00f[7:4] 101 0x65 vbi_data_p7_n24 vdp_line_010[7:4] 102 0x66 vbi_data_p8_n25 vdp_line_011[7:4] 103 0x67 vbi_data_p9 vdp_line_012[7:4] 104 0x68 vbi_data_p10 vdp_line_013[7:4] 105 0x69 vbi_data_p11 vdp_line_014[7:4] 106 0x6a vbi_data_p12_n10 vdp_line_015[7:4] 107 0x6b vbi_data_p13_n11 vdp_line_016[7:4] 108 0x6c vbi_data_p14_n12 vdp_line_017[7:4] 109 0x6d vbi_data_p15_n13 vdp_line_018[7:4] 110 0x6e vbi_data_p16_n14 vdp_line_019[7:4] 111 0x6f vbi_data_p17_n15 vdp_line_01a[7:4] 112 0x70 vbi_data_p18_n16 vdp_line_01b[7:4] 113 0x71 vbi_data_p19_n17 vdp_line_01c[7:4] 114 0x72 vbi_data_p20_n18 vdp_line_01d[7:4] 115 0x73 vbi_data_p21_n19 vdp_line_01e[7:4] 116 0x74 vbi_data_p22_n20 vdp_line_01f[7:4] 117 0x75 vbi_data_p23_n21 vdp_line_020[7:4] 118 0x76 vbi_data_p24_n22 vdp_line_021[7:4] 119 0x77 vbi_data_p318 vdp_linee_00e[3:0] 100 0x64 vbi_data_p319_n286 vdp_line_00f[3:0] 101 0x65 vbi_data_p320_n287 vdp_line_010[3:0] 102 0x66 vbi_data_p321_n288 vdp_line_011[3:0] 103 0x67 vbi_data_p322 vdp_line_012[3:0] 104 0x68 vbi_data_p323 vdp_line_013[3:0] 105 0x69 vbi_data_p324_n272 vdp_line_014[3:0] 106 0x6a vbi_data_p325_n273 vdp_line_015[3:0] 107 0x6b vbi_data_p326_n274 vdp_line_016[3:0] 108 0x6c vbi_data_p327_n275 vdp_line_017[3:0] 109 0x6d vbi_data_p328_n276 vdp_line_018[3:0] 110 0x6e vbi_data_p329_n277 vdp_line_019[3:0] 111 0x6f vbi_data_p330_n278 vdp_line_01a[3:0] 112 0x70 vbi_data_p331_n279 vdp_line_01b[3:0] 113 0x71 vbi_data_p332_n280 vdp_line_01c[3:0] 114 0x72 vbi_data_p333_n281 vdp_line_01d[3:0] 115 0x73 vbi_data_p334_n282 vdp_line_01e[3:0] 116 0x74 vbi_data_p335_n283 vdp_line_01f[3:0] 117 0x75 vbi_data_p336_n284 vdp_line_020[3:0] 118 0x76 vbi_data_p337_n285 vdp_line_021[3:0] 119 0x77 note: full field detection (lines other than vbi lines) of any standard can also be enabled by writing into the registers vbi_data_p24_n22[3:0] and vbi_data_p337_n285[3:0]. so, if vbi_data_p24_n22[3:0] is programmed with any teletext standard, then teletext is decoded off the whole of the odd field. the corresponding register for the even field is vbi_data_p337_n285[3:0]. teletext system identification: vdp assumes that if teletext is present in a video channel, all the teletext lines comply with a single standard system. thus, the line programming using vbi_data_px_ny registers identifies whether the data in line is teletext; the actual standard is identified by the vdp_ttxt_type_man bit. to program the vdp_ttxt_type_man bit, the vdp_ttxt_type_man_enable bit must be set to 1.
ADV7184 rev. 0 | page 51 of 108 vdp_ttxt_type_man_enable enable manual selection of teletext type, address 0x60 [2], user sub map 0 (default)manual programming of the teletext type is disabled. 1manual programming of the teletext type is enabled. vdp_ttxt_type_man [1:0] specify the teletext type, address 0x60 [1:0], user sub map these bits specify the teletext type to be decoded. these bits are functional only if vdp_ttxt_type_man_enable is set to 1. table 67. vdp_ttxt_t ype_man function vdp_ttxt_ type_man [1:0] description 625/50 (pal ) 525/60 (ntsc). 00 (default) teletext-itu- bt.653- 625/50-a. reserved. 01 teletext-itu- bt.653- 625/50-b (wst). teletext-itu-bt.653- 525/60-b. 10 teletext-itu- bt.653- 625/50-c. teletext-itu-bt.653- 525/60-c or eia516 (nabts). 11 teletext-itu- bt.653- 625/50-d. teletext-itu-bt.653- 525/60-d. vdp ancillary data output reading the data back via i 2 c may not be feasible for vbi data standards with high data rates (for example, teletext). an alternative is to place the sliced data in a packet in the line blanking of the digital output ccir656 stream. this is available for all standards sliced by the vdp module. when data has been sliced on a given line, the corresponding ancillary data packet is placed immediately after the next eav code that occurs at the output (that is, data sliced from multiple lines are not buffered up and then emitted in a burst). note that the line number on which the packet is placed differs from the line number on which the data was sliced due to the vertical delay through the comb filters. users can enable or disable the insertion of vdp decoded results into the 656 ancillary streams by using the adf_enable bit. adf_enable enable ancillary data output through 656 stream, address 0x62 [7], user sub map 0 (default)disables insertion of vbi decoded data into ancillary 656 stream. 1enables insertion of vbi decoded data into ancillary 656 stream. the user may select the data identification word (did) and the secondary data identification word (sdid) through programming the adf_did[4:0] and adf_sdid[5:0] bits respectively as explained next. adf_did[4:0] user specified data id word in ancillary data, address 0x62 [4:0], user sub map this bit selects the data id word to be inserted in the ancillary data stream with the data decoded by the vdp. the default value of adf_did [4:0] is 10101. adf_sdid[5:0] user specified secondary data id word in ancillary data, address 0x63 [5:0], user sub map these bits select the secondary data id word to be inserted in the ancillary data stream with the data decoded by the vdp. the default value of adf_sdid [5:0] is 101010. duplicate_adf enable duplication/spreading of ancillary data over y and c buses, address 0x 63 [7], user sub map this bit determines whether the ancillary data is duplicated over both y and c buses or if the data packets are spread between the two channels. 0 (default)the ancillary data packet is spread across the y and c data streams. 1the ancillary data packet is duplicated on the y and c data streams. adf_mode [1:0] determine the ancillary data output mode, address 0x62 [6:5], user sub map these bits determine if the ancillary data output mode is in byte mode or nibble mode. table 68. adf_mode [1:0] description 00 (default) nibble mode. 01 byte mode, no code restrictions. 10 byte mode but 0x00 an d 0xff prevented (0x00 replaced by 0x01, 0xff replaced by 0xfe). 11 reserved.
ADV7184 rev. 0 | page 52 of 108 the ancillary data packet sequence is explained in table 69 and table 70. the nibble output mode is the default mode of output from the ancillary stream when ancillary stream output is enabled. this format is in compliance with itu-r bt.1364. some definitions of the abbreviations used in table 69 and table 70 include: ? ep. even parity for bits b8 to b2. this means that the parity bit ep is set so that an even number of 1s are in bits in b8 to b2, including the parity bit, d8. ? cs. checksum word. the cs word is used to increase confidence of the integrity of the ancillary data packet from the did, sdid, and dc through user data-words (udws). it consists of 10 bits: a 9-bit calculated value and b9 as the inverse of b8. the checksum value b8 to b0 is equal to the 9 lsbs of the sum of the 9 lsbs of the did, sdid, and dc and all udws in the packet. prior to the start of the checksum count cycle all checksum and carry bits are pre-set to zero. any carry resulting from the checksum count cycle is ignored. ? ep . the msb b9 is the inverse ep. this ensures that restricted codes 0x00 and 0xff do not occur. ? line_number [9:0]. the line number of the line that immediately precedes the ancillary data packet. the line number is as per the numbering system in itu-r bt.470. the line number runs from 1 to 625 in a 625 line system and from 1 to 263 in a 525 line system. note the line number on which the packet is output differs from the line number on which the vbi data was sliced due to the vertical delay through the comb filters. ? data count. the data count specifies the number of udws in the ancillary stream for the standard. the total number of user data-words = 4 data count. padding words may be introduced to make the total number of udws divisible by four. table 69. ancillary data in nibble output format byte b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 description 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 ancillary data preamble 3 ep ep 0 i2c_did6_2[4:0] 0 0 did (data identification word) 4 ep ep i2c_sdid7_2[5:0] 0 0 sdid (secondary data identification word) 5 ep ep 0 dc[4:0] 0 0 data count 6 ep ep padding[1:0] vbi_data_std[3:0] 0 0 id0 (user data-word 1) 7 ep ep 0 line_number[9:5] 0 0 id1 (user data-word 2) 8 ep ep even_field line_number[4:0] 0 0 id2 (user data-word 3) 9 ep ep 0 0 0 0 vdp_ttxt_type[1:0] 0 0 id3 (user data-word 4) 10 ep ep 0 0 vbi_word_1[7:4] 0 0 user data-word 5 11 ep ep 0 0 vbi_word_1[3:0] 0 0 user data-word 6 12 ep ep 0 0 vbi_word_2[7:4] 0 0 user data-word 7 13 ep ep 0 0 vbi_word_2[3:0] 0 0 user data-word 8 14 ep ep 0 0 vbi_word_3[7:4] 0 0 user data-word 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . n-3 1 0 0 0 0 0 0 0 0 0 n-2 1 0 0 0 0 0 0 0 0 0 [pad 0x200. these padding words may or may not be present depending on ancillary data type.] user data- word xx n-1 b8 checksum 0 0 cs (checksum word)
ADV7184 rev. 0 | page 53 of 108 table 70. ancillary data in byte output format 1 byte b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 description 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 ancillary data preamble 3 ep ep 0 i2c_did6_2[4:0] 0 0 did 4 ep ep i2c_sdid7_2[5:0] 0 0 sdid 5 ep ep 0 dc[4:0] 0 0 data count 6 ep ep padding[1:0] vbi_data_std[3:0] 0 0 id0 (user data-word 1) 7 ep ep 0 line_number[9:5] 0 0 id1 (user data-word 2) 8 ep ep even_field line_number[4:0] 0 0 id2 (user data-word 3) 9 ep ep 0 0 0 0 vdp_ttxt_type[1:0] 0 0 id3 (user data-word 4) 10 vbi_word_1[7:0] 0 0 user data-word 5 11 vbi_word_2[7:0] 0 0 user data-word 6 12 vbi_word_3[7:0] 0 0 user data-word 7 13 vbi_word_4[7:0] 0 0 user data-word 8 14 vbi_word_5[7:0] 0 0 user data-word 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . n-3 1 0 0 0 0 0 0 0 0 0 n-2 1 0 0 0 0 0 0 0 0 0 [pad 0x200. these padding words may or may not be present depending on ancillary data type.] user data- word xx n-1 b8 checksum 0 0 1 this mode does not fully comply with itu-r bt.1364. structure of vbi words in ancillary data stream each vbi data standard has been split into a clock-run-in (cri), a framing code (fc) and a number of data bytes (n). the data packet in the ancillary stream includes only the fc and data bytes. the vbi_word_x in the ancillary data stream has the following format. table 71. structure of vbi data -words in ancillary stream ancillary data byte number byte type byte description vbi_word_1 fc0 framing code [23:16]. vbi_word_2 fc1 framing code [15:8]. vbi_word_3 fc2 framing code [7:0]. vbi_word_4 db1 1 st data byte. vbi_word_n+3 dbn last (nth) data byte. vdp framing code the length of the actual framing code depends on the vbi data standard. for uniformity, the length of the framing code reported in the ancillary data stream is always 24 bits. for standards with a lesser framing code length, the extra lsb bits are set to 0. the valid length of the framing code can be decoded from the vbi_data_std bit available in id0 (udw 1). the framing code is always reported in the inverse- transmission order. table 72 shows the framing code and its valid length for vbi data standards supported by vdp. example for teletext (b-wst) the framing code byte is 11100100 (0xe4), bits shown in the order of transmission. thus, vbi_word_1 = 0x27, vbi_word_2 = 0x00 and vbi_word_3 = 0x00. translating them into udws in the ancillary data stream, for the nibble mode: udw5 [5:2] = 0010 udw6 [5:2] = 0111 udw7 [5:2] = 0000 (undefined bits made zeros) udw8 [5:2] = 0000 (undefined bits made zeros) udw9 [5:2] = 0000 (undefined bits made zeros) udw10 [5:2] = 0000 (undefined bits made zeros) and for the byte mode: udw5 [9:2] = 0010_0111 udw6 [9:2] = 0000_0000 (undefined bits made zeros) udw7 [9:2] = 0000_0000 (undefined bits made zeros)
ADV7184 rev. 0 | page 54 of 108 data bytes the vbi_word_4 to vbi_word_n+3 contains the data- words that were decoded by the vdp in the transmission order. the position of bits in bytes is in the inverse transmission order. for example, closed caption has two user data bytes as shown in table 77. the data bytes in the ancillary data stream would be: vbi_word_4 = byte1 [7:0] vbi_word_5 = byte2 [7:0] the number of vbi_words for each vbi data standard and the total number of udws in the ancillary data stream is shown in table 73. table 72. framing code sequence for different vbi standards vbi standard length in bits error free framing code bits (in order of transmission ) error free framing code reported by vdp (in reverse order of transmission ) ttxt_system_a (pal) 8 11100111 11100111 ttxt_system_b (pal) 8 11100100 00100111 ttxt_system_b (ntsc) 8 11100100 00100111 ttxt_system_c (pal and ntsc) 8 11100111 11100111 ttxt_system_d (pal and ntsc) 8 11100101 10100111 vps (pal) 16 10001010100011001 1001100101010001 vitc (ntsc and pal) 1 0 0 wss (pal) 24 000111100011110000011111 111110000011110001111000 gemstar_1x (ntsc) 3 001 100 gemstar_2x (ntsc) 11 1001_1011_101 101_1101_1001 ccap (ntsc and pal) 3 001 100 cgms (ntsc) 1 0 0 table 73. total user data-words for different vbi standards 1 vbi standard adf mode framing_code udws vbi data words number of padding words total udws 00 (nibble mode) 6 74 0 84 ttxt_system_a (pal) 01,10 (byte mode) 3 37 0 44 00 (nibble mode) 6 84 2 96 ttxt_system_b (pal) 01,10 (byte mode) 3 42 3 52 00 (nibble mode) 6 68 2 80 ttxt_system_b (ntsc) 01,10 (byte mode) 3 34 3 44 00 (nibble mode) 6 66 0 76 ttxt_system_c (pal and ntsc) 01,10 (byte mode) 3 33 2 42 00 (nibble mode) 6 68 2 80 ttxt_system_d (pal and ntsc) 01,10 (byte mode) 3 34 3 44 00 (nibble mode) 6 26 0 36 vps (pal) 01,10 (byte mode) 3 13 0 20 00 (nibble mode) 6 18 0 28 vitc (ntsc and pal) 01,10 (byte mode) 3 9 0 16 00 (nibble mode) 6 4 2 16 wss (pal) 01,10 (byte mode) 3 2 3 12 00 (nibble mode) 6 4 2 16 gemstar_1x (ntsc) 01,10 (byte mode) 3 2 3 12 00 (nibble mode) 6 8 2 20 gemstar_2x (ntsc) 01,10 (byte mode) 3 4 1 12 00 (nibble mode) 6 4 2 16 ccap (ntsc and pal) 01,10 (byte mode) 3 2 3 12 00 (nibble mode) 6 6 0 16 cgms (ntsc) 01,10 (byte mode) 3 3 + 3 2 12 1 the first four udws are always the id.
ADV7184 rev. 0 | page 55 of 108 i 2 c interface dedicated i 2 c readback registers are available for ccap, cgms, wss, gemstar, vps, pdc/utc and vitc. because teletext is a high data rate standard, data extraction is supported only through the ancillary data packet. the details of these registers and their access procedure are described next. user interface for i 2 c readback registers the vdp decodes all enabled vbi data standards in real time. since the i 2 c access speed is much lower than the decoded rate, when the registers are being accessed they may be updated with data from the next line. in order to avoid this, vdp has a self-clearing clear bit and an available status bit accompanying all the i 2 c readback registers. the user has to clear the i 2 c readback register by writing a high to the clear bit. this resets the state of the available bit to low and indicates that the data in the associated readback registers is not valid. after the vdp decodes the next line of the corresponding vbi data, the decoded data is placed in the i 2 c readback register and the available bit is set to high to indicate that valid data is now available. though the vdp decodes this vbi data in subsequent lines if present, the decoded data is not updated to the readback registers until the clear bit is set high again. however, this data is available through the 656 ancillary data packets. the clear and available bits are in the vdp_clear (0x78, user sub map, write only) and vdp_status (0x78, user sub map, read only) registers. example i 2 c readback procedure the following tasks have to be performed to read one packet (line) of pdc data from the decoder. 1. write 10 to i2c_gs_vps_pdc_utc[1:0] (0x9c, user sub map) to specify that pdc data has to be updated to i 2 c registers. 2. write high to the gs_pdc_vps_utc_clear bit (0x78, user sub map) to enable i 2 c register updating. 3. poll the gs_pdc_vps_utc_avl bit (0x78, user sub map) going high to check the availability of the pdc packets. 4. read the data bytes from the pdc i 2 c registers. to read another line or packet of data the above steps have to be repeated. to read a packet of cc, cgms, or wss data, steps 1 through 3 only are required since they have dedicated registers. vdpcontent-based data update for certain standards like wss, cgms, gemstar, pdc, utc, and vps the information content in the signal transmitted remains the same over numerous lines and the user may want to be notified only when there is a change in the information content or loss of the information content. the user must enable content-based updating for the required standard through the gs_vps_pdc_utc_cb_change and wss_cgms_cb_change bits. thus the available bit shows the availability of that standard only when its content changes. content-based updating also applies to loss of data at the lines where some data was present before. thus, for standards like vps, gemstar, cgms, and wss, if no data arrives in the next four lines programmed, the corresponding available bit in the vdp_status register is set high and the content in the i 2 c registers for that standard is set to zero. the user has to write high to the corresponding clear bit so that when a valid line is decoded after some time, the decoded results are available into the i 2 c registers, with the available status bit set high. if content-based updating is enabled, the available bit is set high (assuming the clear bit was written) in the following cases: ? the data contents change. ? data was being decoded and four lines with no data have been detected. ? no data was being decoded and new data is now being decoded. gs_vps_pdc_utc_cb_change enable content-based updating for gemstar/vps/pdc/utc, address 0x9c [5], user sub map 0disables content-based updating. 1 (default)enables content-based updating. wss_cgms_cb_change enable content-based updating for wss/cgms, address 0x9c [4], user sub map 0disables content-based updating. 1 (default)enables content-based updating. vdpinterrupt-based reading of vdp i 2 c registers some vdp status bits are also linked to the interrupt request controller so that the user does not have to poll the available status bit. the user can configure the video decoder to trigger an interrupt request on the intrq pin in response to the valid data available in i 2 c registers. this function is available for the following data types: cgms or wss: the user can select between triggering an interrupt request each time sliced data is available or triggering an interrupt request only when the sliced data has changed. selection is made via the wss_cgms_cb_change bit.
ADV7184 rev. 0 | page 56 of 108 gemstar, pdc, vps, or utc : the user can select between triggering an interrupt request each time sliced data is available or triggering an interrupt request only when the sliced data has changed. selection is made via the gs_vps_pdc_utc_cb_ change bit. the sequence for the interrupt-based reading of the vdp i 2 c data registers is the following for the ccap standard. 1. user unmasks ccap interrupt mask bit (0x50 bit 0, user sub map = 1). ccap data occurs on the incoming video. vdp slices ccap data and places it in the vdp readback registers. 2. the vdp ccap available bit goes high and the vdp module signals to the interrupt controller to stimulate an interrupt request (for ccap in this case). 3. the user reads the interrupt status bits (user sub map) and sees that new ccap data is available (0x4e bit 0, user sub map = 1). 4. the user writes 1 to the ccap interrupt clear bit (0x4f bit 0, user sub map = 1) in the interrupt i 2 c space (this is a self-clearing bit). this clears the interrupt on the intrq pin but does not have an effect in the vdp i 2 c area. 5. the user reads the ccap data from the vdp i 2 c area. 6. the user writes to a bit, cc_clear in the vdp_status [0] register, (0x78 bit 0, user sub map = 1) to signify the ccap data has been read (=> the vdp ccap can be updated at the next occurrence of ccap). 7. back to step 2. interrupt mask register details the following bits set the interrupt mask on the signal from the vdp vbi data slicer. vdp_ccapd_mskb address 0x50 [0], user sub map 0 (default)disables interrupt on vdp_ccapd_q signal. 1enables interrupt on vdp_ccapd_q signal. vdp_cgms_wss_chngd_mskb address 0x50 [2], user sub map 0 (default)disables interrupt on vdp_cgms_wss_ chngd_q signal. 1enables interrupt on vdp_cgms_wss_chngd_q signal. vdp_gs_vps_pdc_utc_chng_mskb address 0x50 [4], user sub map 0 (default)disables interrupt on vdp_gs_vps_pdc_utc_chng_q signal. 1enables interrupt on vdp_gs_vps_pdc_utc_chng_q signal. vdp_vitc_mskb address 0x50 [6], user sub map 0 (default)disables interrupt on vdp_vitc_q signal. 1enables interrupt on vdp_vitc_q signal. interrupt status register details the following read-only bits contain data detection information from the vdp module from the time the status bit has been last cleared or unmasked. vdp_ccapd_q address 0x4e [0], user sub map 0 (default)ccap data has not been detected. 1ccap data has been detected. vdp_cgms_wss_chngd_q address 0x4e [2], user sub map 0 (default)cgms or wss data has not been detected. 1cgm or wss data has been detected. vdp_gs_vps_pdc_utc_chng_q address 0x4e [4], user sub map 0 (default)gemstar, pdc, utc, or vps data has not been detected. 1gemstar, pdc, utc, or vps data has been detected. vdp_vitc_q address 0x4e [6], user sub map, read only 0 (default)vitc data has not been detected. 1vitc data has been detected. interrupt status clear register details it is not necessary to write 0 to these write-only bits as they automatically reset when they are set (self-clearing). vdp_ccapd_clr address 0x4f [0], user sub map 1clears vdp_ccap_q bit. vdp_cgms_wss_chngd_clr address 0x4f [2], user sub map 1clears vdp_cgms_wss_chngd_q bit. vdp_gs_vps_pdc_utc_chng_clr address 0x4f [4], user sub map 1clears vdp_gs_vps_pdc_utc_chng_q bit. vdp_vitc_clr address 0x4f [6], user sub map 1clears vdp_vitc_q bit.
ADV7184 rev. 0 | page 57 of 108 i 2 c readback registers teletext because teletext is a high data rate standard, the decoded bytes are available only as ancillary data. however, a ttx_avl bit has been provided in i 2 c so that the user can check whether or not the vdp has detected teletext. note that the ttxt_avl bit is a plain status bit and does not use the protocol identified in the i 2 c interface section. ttxt_avl teletext detected status bit, address 0x78 [7], user sub map, read only 0teletext was not detected. 1teletext was detected. wst packet decoding for wst only, the vdp decodes the magazine and row address of wst teletext packets and further decodes the packets 8x4 hamming coded words. this feature can be disabled using wst_pkt_ decod_ disable bit (bit 3, register 0x60, user sub map). the feature is valid for wst only. wst_pkt_decod_disable disable hamming decoding of bytes in wst, address 0x60 [3], user sub map 0enables hamming decoding of wst packets 1 (default)disables hamming decoding of wst packets. for hamming coded bytes, the dehammed nibbles are output along with some error information from the hamming decoder as follows. ? input hamming coded byte: {d3, p3, d2, p2, d1, p1, d0, p0} (bits in decoded order) ? output dehammed byte: {e1, e0, 0, 0, d3, d2, d1, d0} (di C corrected bits, ei error info). table 74. explanation of error bits in the dehammed output byte e[1:0] error information output data bitsin nibble 00 no errors detected ok 01 error in p4 ok 10 double error bad 11 single error found and corrected ok table 75 describes the different wst packets that are decoded. table 75. wst packet description packet byte description 1p st byte mag no. C dehammed byte 4. 2p nd byte row no. C dehammed byte 5. 3 rd byte page no. C dehammed byte 6. 4 th byte page no. C dehammed byte 7. 5 th to 10 th byte control bytes C deha mmed byte 8 to byte 13. header packet (x/00) 11 th to 42 nd byte raw data bytes. 1 st byte mag no. C dehammed byte 4. 2 nd byte row no. C dehammed byte 5. text packets (x/01 to x/25) 3 rd to 42 nd byte raw data bytes. 1 st byte mag no. C dehammed byte 4. 2 nd byte row no. C dehammed byte 5. 3 rd byte desig code. C dehammed byte 6. 4 th byte to 10 th byte dehammed initial teletext page byte 7 to byte 12. 11 th to 23 rd byte utc bytes C dehammed bytes 13 to byte 25. 8/30 (format 1) packet desig code = 0000 or 0001 utc 24 th to 42 nd byte raw status bytes. 1 st byte mag no. C dehammed byte 4. 2 nd byte row no. C dehammed byte 5. 3 rd byte desig code. C dehammed byte 6. 4 th byte to 10 th byte dehammed initial teletext page byte 7 to byte 12. 11 th to 23 rd byte pdc bytes C dehamme d byte 13 to byte 25. 8/30 (format 2) packet desig code = 0010 or 0011 pdc 24 th to 42 nd byte raw status bytes. 1 st byte mag no. C dehammed byte 4. 2 nd byte row no. C dehammed byte 5. 3 rd byte desig code. C dehammed byte 6. x/26, x/27, x/28, x/29, x/30, x/31 1 4 th to 42 nd byte raw data bytes. 1 for x/26, x/28 and m/29, further decoding needs 24x18 hamming decoding. not supported at present.
ADV7184 rev. 0 | page 58 of 108 cgms and wss the cgms and wss data packets convey the same type of information for different video standards. wss is for pal and cgms is for ntsc and hence the cgms and wss readback registers are shared. wss is bi-phase coded; the vdp does a biphase decoding to produce the 14 raw wss bits in the cgms/wss readback i 2 c registers and sets the cgms_wss_avl bit. cgms_wss_clear cgms/wss clear, address 0x78 [2], user sub map, write only, self clearing 1re-initializes the cgms/wss readback registers. cgms_wss_avl cgms/wss available bit, address 0x78 [2], user sub map, read only 0cgms/wss was not detected. 1cgms/wss was detected. cgms_wss_data_0[3:0] address 0x7d [3:0] cgms_wss_data_1[7:0] address 0x7e [7:0] cgms_wss_data_2[7:0] address 0x7f [7:0] user sub map, read only. these bits hold the decoded cgms or wss data. refer to figure 37 and figure 38 for the i 2 c to wss and cgms bit mapping. ccap two bytes of decoded closed caption data are available in the i 2 c registers. the field information of the decoded ccap data can be obtained from the cc_even_field bit (register 0x78). cc_clear closed caption clear, address 0x78 [0] user sub map, write only, self clearing 1re-initializes the ccap readback registers. cc_avl closed caption available, address 0x78 [0], user sub map, read only 0closed captioning was not detected. 1closed captioning was detected. cc_even_field address 0x78 [1], user sub map, read only identifies the field from which the ccap data was decoded. 0closed captioning detected on an odd field. 1closed captioning was detected on an even field. vdp_ccap_data_0 address 0x79 [7:0], user sub map, read only decoded byte 1 of ccap data. vdp_ccap_data_1 address 0x7a [7:0], user sub map, read only decoded byte 2 of ccap data. 05479-037 active video vdp_cgms_wss_ data_1[5:0] vdp_cgms_wss_data_2 run-in sequence start code 0 1 2 3 4 5 6 7 0 1 2 3 4 5 11.0 s 38.4 s 42.5 s figure 37. wss waveform 05479-038 01 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 vdp_cgms_wss_data_1 vdp_cgms_wss_ data_0[3:0] vdp_cgms_wss_data_2 ref +100 ire +70 ire 0 ire ?40 ire 11.2 s 49.1 s 0.5 s crc sequence 2.235 s 20ns figure 38. cgms waveform
ADV7184 rev. 0 | page 59 of 108 table 76. cgms readback registers 1 signal name register location address (user sub map) cgms_wss_data_0[3:0] vdp_cgms_wss_data_0 [3:0] 125 0x7d cgms_wss_data_1[7:0] vdp_cgms_wss_data_1 [7:0] 126 0x7e cgms_wss_data_2[7:0] vdp_cgms_wss_data_2 [7:0] 127 0x7f 1 the register is a readback regi ster; default value does not apply. 0 reference color burst (9 cycles) frequency = f sc = 3.579545mhz amplitude = 40 ire 1 7 cycles of 0.5035mhz (clock run-in) 2 3 4 5 6 7 0 1 2 3 4 5 67 p a r i t y s t a r t p a r i t y vdp_ccap_data_0 33.764 s 10.003 s 10.5 0.25 s 12.91 s 27.382 s 50 ire 40 ire 05479-039 vdp_ccap_data_1 figure 39.ccap waveform and decoded data correlation table 77. ccap readback registers 1 signal name register location address (user sub map) ccap_byte_1[7:0] vdp_ccap_data_0[7:0] 121 0x79 ccap_byte_2[7:0] vdp_ccap_data_1[7:0] 122 0x7a 1 the register is a readback regi ster; default value does not apply. bit0, bit1 bit88, bit89 to vitc waveform 05479-040 figure 40. vitc waveform and decoded data correlation vitc vitc has a sync sequence of 10 in between each data byte. the vdp strips these syncs from the data stream to give out only the data bytes. the vitc results are available in vdp_vitc_data_0 to vdp_vitc_data_8 registers (register 0x92 to register 0x9a, user sub map). the vitc has a crc byte at the end; the in-between syncs are also used in this crc calculation. since the in-between syncs are not given out, the crc is also calculated internally. the calculated crc is also available for the user in vitc_calc_crc register (resister 0x9b, user sub map). once the vdp completes decoding the vitc line, the vitc_data and vitc_calc_crc registers are updated and vitc_avl bit is set. vitc_clear vitc clear, address 0x78 [6], user sub map, write only, self clearing 1re-initializes the vitc readback registers. vitc_avl vitc available, address 0x78 [6], user sub map 0vitc data was not detected. 1vitc data was detected. vitc readback registers see figure 40 for the i 2 c to vitc bit mapping.
ADV7184 rev. 0 | page 60 of 108 table 78. vitc readback registers 1 signal name register location address (user sub map) vitc_data_0[7:0] vdp_vitc_data_0[7:0] (vitc bits [9:2]) 146 0x92 vitc_data_1[7:0] vdp_vitc_data_1[7:0] (vitc bits [19:12]) 147 0x93 vitc_data_2[7:0] vdp_vitc_data_2[7:0] (vitc bits [29:22]) 148 0x94 vitc_data_3[7:0] vdp_vitc_data_3[7:0] (vitc bits [39:32]) 149 0x95 vitc_data_4[7:0] vdp_vitc_data_4[7:0] (vitc bits [49:42]) 150 0x96 vitc_data_5[7:0] vdp_vitc_data_5[7:0] (vitc bits [59:52]) 151 0x97 vitc_data_6[7:0] vdp_vitc_data_6[7:0] (vitc bits [69:62]) 152 0x98 vitc_data_7[7:0] vdp_vitc_data_7[7:0] (vitc bits [79:72]) 153 0x99 vitc_data_8[7:0] vdp_vitc_data_8[7:0] (vitc bits [89:82]) 154 0x9a vitc_calc_crc[7:0] vdp_vi tc_calc_crc[7:0] 155 0x9b 1 the register is a readback regi ster; default value does not apply. vps/pdc/utc/gemstar the readback registers for vps, pdc and utc have been shared. gemstar is a high data rate standard and so is available only through the ancillary stream; however, for evaluation purposes any one line of gemstar is available through i 2 c registers sharing the same register space as pdc, utc, and vps. thus only one standard out of vps, pdc, utc, and gemstar can be read through the i 2 c at a time. the user has to program i2c_gs_vps_pdc_utc[1:0] (register address 0x9c, user sub map)to identify the data that should be made available in the i 2 c registers. i2c_gs_vps_pdc_utc (vdp) [1:0] address 0x9c [6:5], user sub map specifies which standard result to be available for i 2 c readback. table 79. i2c_gs_vps_pdc_utc[1:0] function i2c_gs_vps_pdc_utc[1:0] description 00 (default) gemstar 1x/2x. 01 vps. 10 pdc. 11 utc. gs_pdc_vps_utc_clear gs/pdc/vps/utc clear, address 0x78 [4], user sub map, write only, self clearing 1re-initializes the gs/pdc/vps/utc data readback registers. gs_pdc_vps_utc_avl gs/pdc/vps/utc available , address 0x78 [4], user sub map, read only 0one of gs, pdc, vps or utc data was not detected. 1one of gs, pdc, vps, or utc data was detected. vdp_gs_vps_pdc_utc readback registers see table 80. vps the vps data bits are bi-phase decoded by the vdp. the decoded data is available in both the ancillary stream and in the i 2 c readback registers. vps decoded data is available in the vdp_gs_vps_pdc_utc_0 to vdp_vps_pdc_utc_12 registers (addresses 0x84 C 0x90, user sub map). the gs_vps_ pdc_utc_avl bit is set if the user had programmed i2c_gs_vps_pdc_utc to 01, as explained in table 79. gemstar the gemstar decoded data is made available in the ancillary stream and any one line of gemstar is also available in i 2 c registers for evaluation purposes. in order to obtain gemstar results in i 2 c registers, the user has to program i2c_gs_vps_pdc_utc to 00, as explained in table 79. vdp supports auto detection of gemstar standard between gemstar 1 or gemstar 2 and decodes accordingly. for this auto detection mode to work the user has to set auto_detect_gs_type i 2 c bit (register 0x61, user sub map) and program the decoder to decode gemstar 2 on the required lines through line programming. the type of gemstar decoded can be determined by observing the bit gs_data_type bit (register 0x78, user sub map). auto_detect_gs_type, address 0x61 [4], user sub map 0 (default)disables autodetection of gemstar type. 1enables autodetection. gs_data_type, address 0x78 [5], user sub map, read only identifies the decoded gemstar data type. 0gemstar 1 mode is detected. read 2 data bytes from 0x84. 1gemstar 2 mode is detected. read 4 data bytes from 0x84. the gemstar data that is available in the i 2 c register could be from any line of the input video on which gemstar was decoded. to read the gemstar data on a particular video line, the user should use the manual configuration as described in table 65 and table 66 and enable gemstar decoding on the required line only.
ADV7184 rev. 0 | page 61 of 108 table 80. gs /vps/pdc/utc readback registers 1 address (user sub map) signal name register location dec hex gs_vps_pdc_utc_byte_0[7:0] vdp_gs_vps_pdc_utc_0[7:0] 132d 0x84 gs_vps_pdc_utc_byte_1[7:0] vdp_gs_vps_pdc_utc_1[7::0] 133d 0x85 gs_vps_pdc_utc_byte_2[7:0] vdp_gs_vps_pdc_utc_2[7:0] 134d 0x86 gs_vps_pdc_utc_byte_3[7:0] vdp_gs_vps_pdc_utc_3[7:0] 135d 0x87 vps_pdc_utc_byte_4[7:0] vdp_vps_pdc_utc_4[7:0] 136d 0x88 vps_pdc_utc_byte_5[7:0] vdp_vps_pdc_utc_5[7:0] 137d 0x89 vps_pdc_utc_byte_6[7:0] vdp_vps_pdc_utc_6[7:0] 138d 0x8a vps_pdc_utc_byte_7[7:0] vdp_vps_pdc_utc_7[7:0] 139d 0x8b vps_pdc_utc_byte_8[7:0] vdp_vps_pdc_utc_8[7:0] 140d 0x8c vps_pdc_utc_byte_9[7:0] vdp_vps_pdc_utc_9[7:0] 141d 0x8d vps_pdc_utc_byte_10[7:0] vdp_vps_pdc_utc_10[7:0] 142d 0x8e vps_pdc_utc_byte_11[7:0] vdp_vps_pdc_utc_11[7:0] 143d 0x8f vps_pdc_utc_byte_12[7:0] vdp_vps_pdc_utc_12[7:0] 144d 0x90 1 the register is a readback regi ster; default value does not apply. pdc/utc pdc and utc are data transmitted through teletext packet 8/30 format 2 (magazine 8, row 30, design_code 2 or 3), and packet 8/30 format 1 (magazine 8, row 30, design_code 0 or 1). hence, if pdc or utc data is to be read through i 2 c, the corresponding teletext standard (wst or pal system b) should be decoded by vdp. the whole teletext decoded packet is output on the ancillary data stream. the user can look for the magazine number, row number and design_code and qualify the data as pdc, utc or none of these. if pdc/utc packets have been identified, byte 0 to byte 12 are updated to the gs_vps_pdc_utc_0 to vps_pdc_utc_12 registers, and the gs_vps_pdc_utc_avl bit set. the full packet data is also available in the ancillary data format. note that the data available in the i 2 c register depends on the status of the wst_pkt_decode_disable bit (bit 3, subaddress 0x60, user sub map). vbi system 2 the user has an option of using a different vbi data slicer called vbi system 2. this data slicer is used to decode gemstar and closed caption vbi signals only. using this system, the gemstar data is only available in the ancillary data stream. a special mode enables one line of data to be read back via i 2 c. for details on how to get i 2 c readback when using the vbi system 2 data slicer, see the adi applications note on ADV7184 vbi processing. gemstar data recovery the gemstar-compatible data recovery block (gscd) supports 1 and 2 data transmissions. in addition, it can serve as a closed caption decoder. gemstar-compatible data transmissions can occur only in ntsc. closed caption data can be decoded in both pal and ntsc. the block is configured via i 2 c in the following ways: ? gdecel[15:0] allows data recovery on selected video lines on even fields to be enabled and disabled. ? gdecol[15:0] enables the data recovery on selected lines for odd fields. ? gdecad configures the way in which data is embedded in the video data stream. the recovered data is not available through i 2 c, but is inserted into the horizontal blanking period of an itu-r bt656- compatible data stream. the data format is intended to comply with the recommendation by the international telecommunications union, itu-r bt.1364. for more information, see the itu website at www.itu.ch. see figure 41. gde_sel_old_adf, address 0x4c [3], user map the ADV7184 has a new ancillary data output block that can be used by the vdp data slicer and the vbi system 2 data slicer. the new ancillary data formatter is used by setting gde_sel_old_adf = 0 (this is the default setting). if this bit is set low, refer to table 69 and table 70 for information about how the data is packaged in the ancillary data stream. to use the old ancillary data formatter (to be backward- compatible with the adv7183b), set gde_sel_old_adf = 1. the ancillary data format in this section refers to the adv7183b- compatible ancillary data formatter. 0 (default)enables new ancillary data system (for use with vdp and vbi system 2). 1enables old ancillary data system (for use with vbi system 2 only; adv7183b-compatible).
ADV7184 rev. 0 | page 62 of 108 the format of the data packet depends on the following criteria: ? transmission is 1 or 2. ? data is output in 8-bit or 4-bit format (see the description of the gdecad gemstar decode ancillary data format, address 0x4c [0] bit). ? data is closed caption (ccap) or gemstar-compatible. data packets are output if the corresponding enable bit is set (see the gdecel[15:0] and gdec ol[15:0] descriptions), and if the decoder detects the presence of data. this means that for video lines where no data has been decoded, no data packet is output even if the corresponding line enable bit is set. each data packet starts immediately after the eav code of the preceding line. figure 41 and table 81 show the overall structure of the data packet. entries within the packet are as follows: ? fixed preamble sequence of 0x00, 0xff, 0xff. ? data identification word (did). the value for the did marking a gemstar or ccap data packet is 0x140 (10-bit value). ? secondary data identification word (sdid), which contains information about the video line from which data was retrieved, whether the gemstar transmission was of 1 or 2 format, and whether it was retrieved from an even or odd field. ? data count byte, giving the number of user data-words that follow. ? user data section. ? optional padding to ensure that the length of the user data-word section of a packet is a multiple of four bytes (requirement as set in itu-r bt.1364). ? checksum byte. table 81 lists the values within a generic data packet that is output by the ADV7184 in 8-bit format. 05479-045 00 ff ff did sdid data count user data optional padding bytes check sum secondary data identification preamble for ancillary data data identification user data (4 or 8 words) figure 41. gemstar and ccap embedded data packet (generic) table 81. generic data output packet byte d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] description 0 0 0 0 0 0 0 0 0 0 0 fixed preamble 1 1 1 1 1 1 1 1 1 1 1 fixed preamble 2 1 1 1 1 1 1 1 1 1 1 fixed preamble 3 0 1 0 1 0 0 0 0 0 0 did 4 ep ep ef 2x line[3:0] 0 0 sdid 5 ep ep 0 0 0 0 dc[1] dc[0] 0 0 data count (dc) 6 ep ep 0 0 word1[7:4] 0 0 user data-words 7 ep ep 0 0 word1[3:0] 0 0 user data-words 8 ep ep 0 0 word2[7:4] 0 0 user data-words 9 ep ep 0 0 word2[3:0] 0 0 user data-words 10 ep ep 0 0 word3[7:4] 0 0 user data-words 11 ep ep 0 0 word3[3:0] 0 0 user data-words 12 ep ep 0 0 word4[7:4] 0 0 user data-words 13 ep ep 0 0 word4[3:0] 0 0 user data-words 14 cs[8] cs[8] cs[7] cs[6] cs[5] cs[4] cs[3] cs[2] 0 0 checksum
ADV7184 rev. 0 | page 63 of 108 table 82. data byte allocation 2 raw information bytes retrieved from the video line gdecad user data-words (including padding) padding bytes dc[1:0] 1 4 0 8 0 10 1 4 1 4 0 01 0 2 0 4 0 01 0 2 1 4 2 01 gemstar bit names ? did. the data identification value is 0x140 (10-bit value). care has been taken that in 8-bit systems, the two lsbs do not carry vital information. ? ep and ep . the ep bit is set to ensure even parity on the data-word d[8:0]. even parity means there is always an even number of 1s within the d[8:0] bit arrangement. this includes the ep bit. ep describes the logic inverse of ep and is output on d[9]. the ep is output to ensure that the reserved codes of 00 and ff cannot happen. ? ef. even field identifier. ef = 1 indicates that the data was recovered from a video line on an even field. ? 2x. this bit indicates whether the data sliced was in gemstar 1 or 2 format. a high indicates 2 format. ? line[3:0]. this entry provides a code that is unique for each of the possible 16 source lines of video from which gemstar data may have been retrieved. refer to table 91 and table 92. ? dc[1:0]. data count value. the number of udws in the packet divided by 4. the number of udws in any packet must be an integral number of 4. padding is required at the end, if necessary, as set in itu-r bt.1364. see table 82. ? the 2x bit determines whether the raw information retrieved from the video line was 2 or 4 bytes. the state of the gdecad bit affects whether the bytes are transmitted straight (that is, two bytes transmitted as two bytes) or whether they are split into nibbles (that is, two bytes transmitted as four half bytes). padding bytes are then added where necessary. ? cs[8:2]. the checksum is provided to determine the integrity of the ancillary data packet. it is calculated by summing up d[8:2] of did, sdid, the data count byte, and all udws, and ignoring any overflow during the summation. since all data bytes that are used to calculate the checksum have their 2 lsbs set to 0, the cs[1:0] bits are also always 0. cs[8] describes the logic inversion of cs[8]. the value cs[8] is included in the checksum entry of the data packet to ensure that the reserved values of 0x00 and 0xff do not occur. table 83 to table 88 outline the possible data packages. gemstar 2 format, half-byte output mode half-byte output mode is selected by setting cdecad = 0; full- byte output mode is selected by setting cdecad = 1. see the gdecad gemstar decode ancillary data format, address 0x4c [0] section. gemstar 1 format half-byte output mode is selected by setting cdecad = 0, full- byte output mode is selected by setting cdecad = 1. see the gdecad gemstar decode ancillary data format, address 0x4c [0] section.
ADV7184 rev. 0 | page 64 of 108 table 83. gemstar 2 data, half-byte mode byte d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] description 0 0 0 0 0 0 0 0 0 0 0 fixed preamble 1 1 1 1 1 1 1 1 1 1 1 fixed preamble 2 1 1 1 1 1 1 1 1 1 1 fixed preamble 3 0 1 0 1 0 0 0 0 0 0 did 4 ep ep ef 1 line[3:0] 0 0 sdid 5 ep ep 0 0 0 0 1 0 0 0 data count 6 ep ep 0 0 gemstar word1[7:4] 0 0 user data-words 7 ep ep 0 0 gemstar word1[3:0] 0 0 user data-words 8 ep ep 0 0 gemstar word2[7:4] 0 0 user data-words 9 ep ep 0 0 gemstar word2[3:0] 0 0 user data-words 10 ep ep 0 0 gemstar word3[7:4] 0 0 user data-words 11 ep ep 0 0 gemstar word3[3:0] 0 0 user data-words 12 ep ep 0 0 gemstar word4[7:4] 0 0 user data-words 13 ep ep 0 0 gemstar word4[3:0] 0 0 user data-words 14 cs[8] cs[8] cs[7] cs[6] cs[5] cs[4] cs [3] cs[2] cs[1] cs[0] checksum table 84. gemstar 2 data, full-byte mode byte d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] description 0 0 0 0 0 0 0 0 0 0 0 fixed preamble 1 1 1 1 1 1 1 1 1 1 1 fixed preamble 2 1 1 1 1 1 1 1 1 1 1 fixed preamble 3 0 1 0 1 0 0 0 0 0 0 did 4 ep ep ef 1 line[3:0] 0 0 sdid 5 ep ep 0 0 0 0 0 1 0 0 data count 6 gemstar word1[7:0] 0 0 user data-words 7 gemstar word2[7:0] 0 0 user data-words 8 gemstar word3[7:0] 0 0 user data-words 9 gemstar word4[7:0] 0 0 user data-words 10 cs[8] cs[8] cs[7] cs[6] cs[5] cs[4] cs [3] cs[2] cs[1] cs[0] checksum table 85. gemstar 1 data, half-byte mode byte d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] description 0 0 0 0 0 0 0 0 0 0 0 fixed preamble 1 1 1 1 1 1 1 1 1 1 1 fixed preamble 2 1 1 1 1 1 1 1 1 1 1 fixed preamble 3 0 1 0 1 0 0 0 0 0 0 did 4 ep ep ef 0 line[3:0] 0 0 sdid 5 ep ep 0 0 0 0 0 1 0 0 data count 6 ep ep 0 0 gemstar word1[7:4] 0 0 user data-words 7 ep ep 0 0 gemstar word1[3:0] 0 0 user data-words 8 ep ep 0 0 gemstar word2[7:4] 0 0 user data-words 9 ep ep 0 0 gemstar word2[3:0] 0 0 user data-words 10 cs[8] cs[8] cs[7] cs[6] cs[5] cs[4] cs [3] cs[2] cs[1] cs[0] checksum
ADV7184 rev. 0 | page 65 of 108 table 86. gemstar 1 data, full-byte mode byte d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] description 0 0 0 0 0 0 0 0 0 0 0 fixed preamble 1 1 1 1 1 1 1 1 1 1 1 fixed preamble 2 1 1 1 1 1 1 1 1 1 1 fixed preamble 3 0 1 0 1 0 0 0 0 0 0 did 4 ep ep ef 0 line[3:0] 0 0 sdid 5 ep ep 0 0 0 0 0 1 0 0 data count 6 gemstar word1[7:0] 0 0 user data-words 7 gemstar word2[7:0] 0 0 user data-words 8 1 0 0 0 0 0 0 0 0 0 udw padding 0x200 9 1 0 0 0 0 0 0 0 0 0 udw padding 0x200 10 cs[8] cs[8] cs[7] cs[6] cs[5] cs[4] cs [3] cs[2] cs[1] cs[0] checksum table 87. ntsc ccap data, half-byte mode byte d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] description 0 0 0 0 0 0 0 0 0 0 0 fixed preamble 1 1 1 1 1 1 1 1 1 1 1 fixed preamble 2 1 1 1 1 1 1 1 1 1 1 fixed preamble 3 0 1 0 1 0 0 0 0 0 0 did 4 ep ep ef 0 1 0 1 1 0 0 sdid 5 ep ep 0 0 0 0 0 1 0 0 data count 6 ep ep 0 0 ccap word1[7:4] 0 0 user data-words 7 ep ep 0 0 ccap word1[3:0] 0 0 user data-words 8 ep ep 0 0 ccap word2[7:4] 0 0 user data-words 9 ep ep 0 0 ccap word2[3:0] 0 0 user data-words 10 cs[8] cs[8] cs[7] cs[6] cs[5] cs[4] cs [3] cs[2] cs[1] cs[0] checksum table 88. ntsc ccap data, full-byte mode byte d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] description 0 0 0 0 0 0 0 0 0 0 0 fixed preamble 1 1 1 1 1 1 1 1 1 1 1 fixed preamble 2 1 1 1 1 1 1 1 1 1 1 fixed preamble 3 0 1 0 1 0 0 0 0 0 0 did 4 ep ep ef 0 1 0 1 1 0 0 sdid 5 ep ep 0 0 0 0 0 1 0 0 data count 6 ccap word1[7:0] 0 0 user data-words 7 ccap word2[7:0] 0 0 user data-words 8 1 0 0 0 0 0 0 0 0 0 udw padding 0x200 9 1 0 0 0 0 0 0 0 0 0 udw padding 0x200 10 cs[8] cs[8] cs[7] cs[6] cs[5] cs[4] cs [3] cs[2] cs[1] cs[0] checksum
ADV7184 rev. 0 | page 66 of 108 table 89. pal ccap data, half-byte mode byte d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] description 0 0 0 0 0 0 0 0 0 0 0 fixed preamble 1 1 1 1 1 1 1 1 1 1 1 fixed preamble 2 1 1 1 1 1 1 1 1 1 1 fixed preamble 3 0 1 0 1 0 0 0 0 0 0 did 4 ep ep ef 0 1 0 1 0 0 0 sdid 5 ep ep 0 0 0 0 0 1 0 0 data count 6 ep ep 0 0 ccap word1[7:4] 0 0 user data-words 7 ep ep 0 0 ccap word1[3:0] 0 0 user data-words 8 ep ep 0 0 ccap word2[7:4] 0 0 user data-words 9 ep ep 0 0 ccap word2[3:0] 0 0 user data-words 10 cs[8] cs[8] cs[7] cs[6] cs[5] cs[4] cs [3] cs[2] cs[1] cs[0] checksum table 90. pal ccap data, full-byte mode byte d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] description 0 0 0 0 0 0 0 0 0 0 0 fixed preamble 1 1 1 1 1 1 1 1 1 1 1 fixed preamble 2 1 1 1 1 1 1 1 1 1 1 fixed preamble 3 0 1 0 1 0 0 0 0 0 0 did 4 ep ep ef 0 1 0 1 0 0 0 sdid 5 ep ep 0 0 0 0 0 1 0 0 data count 6 ccap word1[7:0] 0 0 user data-words 7 ccap word2[7:0] 0 0 user data-words 8 1 0 0 0 0 0 0 0 0 0 udw padding 200h 9 1 0 0 0 0 0 0 0 0 0 udw padding 200h 10 cs[8] cs[8] cs[7] cs[6] cs[5] cs[4] cs [3] cs[2] cs[1] cs[0] checksum ntsc ccap data half-byte output mode is selected by setting cdecad = 0, the full-byte mode is enabled by cdecad = 1. see the gdecad gemstar decode ancillary data format, address 0x4c [0] section. the data packet formats are shown in table 87 and table 88. only closed caption data can be embedded in the output data stream. ntsc closed caption data is sliced on line 21d on even and odd fields. the corresponding enable bit has to be set high. see the gdecad gemstar decode ancillary data format, address 0x4c [0] and gdecol[15:0] gemstar decoding odd lines, address 0x4a [7:0]; address 0x4b [7:0] sections. pa l c c a p d at a half-byte output mode is selected by setting cdecad = 0, full- byte output mode is selected by setting cdecad = 1. see the gdecad gemstar decode ancillary data format, address 0x4c [0] section. table 89 and table 90 list the bytes of the data packet. only closed caption data can be embedded in the output data stream. pal closed caption data is sliced from line 22 and line 335. the corresponding enable bits have to be set. see the gdecel[15:0] gemstar decoding even lines, address 0x48 [7:0]; address 0x49 [7:0] and gdecol[15:0] gemstar decoding odd lines, address 0x4a [7:0]; address 0x4b [7:0] sections. gdecel[15:0] gemstar decoding even lines, address 0x48 [7:0]; address 0x49 [7:0] the 16 bits of the gdecel[15:0] are interpreted as a collection of 16 individual line decode enable signals. each bit refers to a line of video in an even field. setting the bit enables the decoder block trying to find gemstar or closed caption-compatible data on that particular line. setting the bit to 0 prevents the decoder from trying to retrieve data. see table 91 and table 92. to retrieve closed caption data services on ntsc (line 284), gdecel[11] must be set. to retrieve closed caption data services on pal (line 335), gdecel[14] must be set. the default value of gdecel[15:0] is 0x0000. this setting instructs the decoder not to attempt to decode gemstar or ccap data from any line in the even field. the user should only enable gemstar slicing on lines where vbi data is expected.
ADV7184 rev. 0 | page 67 of 108 table 91. ntsc line enable bits and corresponding line numbering line[3:0] line number (itu-r bt.470) enable bit comment 0 10 gdecol[0] gemstar 1 11 gdecol[1] gemstar 2 12 gdecol[2] gemstar 3 13 gdecol[3] gemstar 4 14 gdecol[4] gemstar 5 15 gdecol[5] gemstar 6 16 gdecol[6] gemstar 7 17 gdecol[7] gemstar 8 18 gdecol[8] gemstar 9 19 gdecol[9] gemstar 10 20 gdecol[10] gemstar 11 21 gdecol[11] gemstar or closed caption 12 22 gdecol[12] gemstar 13 23 gdecol[13] gemstar 14 24 gdecol[14] gemstar 15 25 gdecol[15] gemstar 0 273 (10) gdecel[0] gemstar 1 274 (11) gdecel[1] gemstar 2 275 (12) gdecel[2] gemstar 3 276 (13) gdecel[3] gemstar 4 277 (14) gdecel[4] gemstar 5 278 (15) gdecel[5] gemstar 6 279 (16) gdecel[6] gemstar 7 280 (17) gdecel[7] gemstar 8 281 (18) gdecel[8] gemstar 9 282 (19) gdecel[9] gemstar 10 283 (20) gdecel[10] gemstar 11 284 (21) gdecel[11] gemstar or closed caption 12 285 (22) gdecel[12] gemstar 13 286 (23) gdecel[13] gemstar 14 287 (24) gdecel[14] gemstar 15 288 (25) gdecel[15] gemstar gdecol[15:0] gemstar decoding odd lines, address 0x4a [7:0]; address 0x4b [7:0] the 16 bits of the gdecol[15:0] form a collection of 16 individual line decode enable signals. see table 91 and tabl e 9 2. to retrieve closed caption data services on ntsc (line 21), gdecol[11] must be set. to retrieve closed caption data services on pal (line 22), gdecol[14] must be set. the default value of gdec0l[15:0] is 0x0000. this setting instructs the decoder not to attempt to decode gemstar or ccap data from any line in the odd field. the user should only enable gemstar slicing on lines where vbi data is expected. gdecad gemstar decode ancillary data format, address 0x4c [0] the decoded data from gemstar-compatible transmissions or closed caption transmission is inserted into the horizontal blanking period of the respective line of video. a potential problem can arise if the retrieved data bytes have the value 0x00 or 0xff. in an itu-r bt.656-compatible data stream, those values are reserved and used only to form a fixed preamble. the gdecad bit allows the data to be inserted into the horizontal blanking period in two ways: ? insert all data straight into the data stream, even the reserved values of 0x00 and 0xff, if they occur. this may violate the output data format specification itu-r bt.1364. ? split all data into nibbles and insert the half-bytes over double the number of cycles in a 4-bit format. 0 (default)the data is split into half-bytes and inserted. 1the data is output straight in 8-bit format.
ADV7184 rev. 0 | page 68 of 108 table 92. pal line enable bits and corresponding line numbering line[3:0] line number (itu-r bt.470) enable bit comment 12 8 gdecol[0] not valid 13 9 gdecol[1] not valid 14 10 gdecol[2] not valid 15 11 gdecol[3] not valid 0 12 gdecol[4] not valid 1 13 gdecol[5] not valid 2 14 gdecol[6] not valid 3 15 gdecol[7] not valid 4 16 gdecol[8] not valid 5 17 gdecol[9] not valid 6 18 gdecol[10] not valid 7 19 gdecol[11] not valid 8 20 gdecol[12] not valid 9 21 gdecol[13] not valid 10 22 gdecol[14] closed caption 11 23 gdecol[15] not valid 12 321 (8) gdecel[0] not valid 13 322 (9) gdecel[1] not valid 14 323 (10) gdecel[2] not valid 15 324 (11) gdecel[3] not valid 0 325 (12) gdecel[4] not valid 1 326 (13) gdecel[5] not valid 2 327 (14) gdecel[6] not valid 3 328 (15) gdecel[7] not valid 4 329 (16) gdecel[8] not valid 5 330 (17) gdecel[9] not valid 6 331 (18) gdecel[10] not valid 7 332 (19) gdecel[11] not valid 8 333 (20) gdecel[12] not valid 9 334 (21) gdecel[13] not valid 10 335 (22) gdecel[14] closed caption 11 336 (23) gdecel[15] not valid letterbox detection incoming video signals may conform to different aspect ratios (16:9 wide screen or 4:3 standard). for certain transmissions in the wide screen format, a digital sequence (wss) is transmitted with the video signal. if a wss sequence is provided, the aspect ratio of the video can be derived from the digitally decoded bits wss contains. in the absence of a wss sequence, letterbox detection may be used to find wide screen signals. the detection algorithm examines the active video content of lines at the start and end of a field. if black lines are detected, this may indicate that the currently shown picture is in wide screen format. the active video content (luminance magnitude) over a line of video is summed together. at the end of a line, this accumulated value is compared with a threshold and a decision is made as to whether or not a particular line is black. the threshold value needed may depend on the type of input signal; some control is provided via lb_th[4:0]. detection at the start of a field the ADV7184 expects a section of at least six consecutive black lines of video at the top of a field. once those lines are detected, register lb_lct[7:0] reports back the number of black lines that were actually found. by default, the ADV7184 starts looking for those black lines in sync with the beginning of active video, for example, straight after the last vbi video line. lb_sl[3:0] allows the user to set the start of letterbox detection from the beginning of a frame on a line-by-line basis. the detection window closes in the middle of the field. detection at the end of a field the ADV7184 expects at least six continuous lines of black video at the bottom of a field before reporting the number of lines actually found via the lb_lcb[7:0] value. the activity window for letterbox detection (end of field) starts in the middle of an active field. its end is programmable via lb_el[3:0]. detection at the midrange some transmissions of wide screen video include subtitles within the lower black box. if the ADV7184 finds at least two black lines followed by some more nonblack video, for example, the subtitle, followed by the remainder of the bottom black block, it reports a midcount via lb_lcm[7:0]. if no subtitles are found, lb_lcm[7:0] reports the same number as lb_lcb[7:0]. there is a 2-field delay in the reporting of any line count parameters. there is no letterbox detected bit. read the lb_lct[7:0] and lb_lcb[7:0] register values to conclude whether or not the letterbox-type video is present in software. lb_lct[7:0] letterbox line count top, address 0x9b [7:0]; lb_lcm[7:0] letterbox line count mid, address 0x9c [7:0]; lb_lcb[7:0] letterbox line count bottom, address 0x9d [7:0] table 93. lb_lcx access information 1 signal name address lb_lct[7:0] 0x9b lb_lcm[7:0] 0x9c lb_lcb[7:0] 0x9d 1 this register is a readback regi ster; default value does not apply.
ADV7184 rev. 0 | page 69 of 108 lb_th[4:0] letterbox threshold control, address 0xdc [4:0] table 94. lb_th function lb_th[4:0] description 01100 (default) default threshold for detection of black lines. 01101 to 10000 increase threshold (need larger active video content before identifying nonblack lines). 00000 to 01011 decrease threshold (even small noise levels can cause the detection of nonblack lines). lb_sl[3:0] letterbox start line, address 0xdd [7:4] the lb_sl[3:0] bits are set at 0100 by default. for an ntsc signal, this window is from line 23 to line 286. by changing the bits to 0101, the detection window starts on line 24 and ends on line 287. lb_el[3:0] letterbox end line, address 0xdd [3:0] the lb_el[3:0] bits are set at 1101 by default. this means that letterbox detection window ends with the last active video line. for an ntsc signal, this window is from line 262 to line 525. by changing the bits to 1100, the detection window starts on line 261 and ends on line 254. if compensation filter iffiltsel[2:0] if filter select address 0xf8 [2:0] the iffiltsel[2:0] register allows the user to compensate for saw filter characteristics on a composite input as would be observed on tuner outputs. figure 42 and figure 43 show if filter compensation for ntsc and pal. the options for this feature are as follows: ? bypass mode (default) ? ntscconsists of three filter characteristics ? palconsists of three filter characteristics 05479-046 frequency (mhz) 2.0 4.0 3.5 3.0 2.5 5.0 4.5 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 amplitude (db) figure 42. ntsc if compensation filter responses 05479-047 frequency (mhz) 3.0 5.0 4.5 4.0 3.5 6.0 5.5 ?8 ?6 ?4 ?2 0 2 4 6 amplitude (db) figure 43. pal if compensation filter responses see table 102 for programming details. i 2 c interrupt system the ADV7184 has a comprehensive interrupt register set. this map is located in the user sub map. see table 103 for details of the interrupt register map. figure 46 describes how to access this map. interrupt request output operation when an interrupt event occurs, the interrupt pin intrq goes low with a programmable duration given by intrq_dur_sel[1:0] intrq_dursel[1:0], interrupt duration select address 0x40 [7:6], user sub map table 95. intrq_dur_sel intrq_dursel[1:0] description 00 (default) 3 xtal periods. 01 15 xtal periods. 10 63 xtal periods. 11 active until cleared. when the active-until-cleared interrupt duration is selected, and the event that caused the interrupt is no longer in force, the interrupt persists until it is masked or cleared. for example, if the ADV7184 loses lock, an interrupt is gener- ated and the intrq pin goes low. if the ADV7184 returns to the locked state, intrq continues to drive low until the sd_lock bit is either masked or cleared.
ADV7184 rev. 0 | page 70 of 108 interrupt drive level the ADV7184 resets with open drain enabled and all interrupts masked off. therefore intrq is in a high impedance state after reset. 01 or 10 has to be written to intrq_op_sel[1:0] for a logic level to be driven out from the intrq pin. it is also possible to write to a register in the ADV7184 that manually asserts the intrq pin. this bit is mpu_stim_intrq. intrq_op_sel[1:0], interrupt duration select address 0x40 [1:0], user sub map table 96. intrq_op_sel intrq_op_sel[1:0] description 00 (default) open drain. 01 drive low when active. 10 drive high when active. 11 reserved. multiple interrupt events if interrupt event 1 occurs and then interrupt event 2 occurs before the system controller has cleared or masked interrupt event 1, the ADV7184 does not generate a second interrupt signal. the system controller should check all unmasked interrupt status bits since more than one may be active. macrovision interrupt selection bits the user can select between pseudo sync pulse and color stripe detection as follows: mv_intrq_sel[1:0], macrovision interrupt selection bits address 0x40 [5:4], user sub map table 97. mv_intrq_sel mv_intrq_sel [1:0] description 00 reserved. 01 (default) pseudo sync only. 10 color stripe only. 11 either pseudo sync or color stripe. additional information relating to the interrupt system is detailed in table 104.
ADV7184 rev. 0 | page 71 of 108 pixel port configuration the ADV7184 has a very flexible pixel port that can be config- ured in a variety of formats to accommodate downstream ics. table 98 and table 99 summarize the various functions that the ADV7184s pins can have in different modes of operation. the ordering of components (cr vs. cb, cha/b/c, for example) can be changed. refer to the swpc swap pixel cr/cb, address 0x27 [7] section. table 98 indicates the default positions for the cr/cb components. of_sel[3:0] output format selection, address 0x03 [5:2] the modes in which the ADV7184 pixel port can be configured are under the control of of_sel[3:0]. see table 99 for details. the default llc frequency output on the llc1 pin is approxi- mately 27 mhz. for modes that operate with a nominal data rate of 13.5 mhz (0001, 0010), the clock frequency on the llc1 pin stays at the higher rate of 27 mhz. for information on outputting the nominal 13.5 mhz clock on the llc1 pin, see the llc_pad_sel[2:0] llc1 output selection, address 0x8f [6:4] section. swpc swap pixel cr/cb, address 0x27 [7] 0 (default)no swapping is allowed. 1the cr and cb values can be swapped. llc_pad_sel[2:0] llc1 output selection, address 0x8f [6:4] the following i 2 c write allows the user to select between llc1 (nominally at 27 mhz) and llc2 (nominally at 13.5 mhz). the llc2 signal is useful for llc2-compatible wide bus (16-bit) output modes. see the of_sel[3:0] output format selection, address 0x03 [5:2] section for additional information. the llc2 signal and data on the data bus are synchronized. by default, the rising edge of llc1/llc2 is aligned with the y data; the falling edge occurs when the data bus holds c data. the polarity of the clock, and therefore the y/c assignments to the clock edges, can be altered by using the polarity llc pin. 000 (default)the output is nominally 27 mhz llc on the llc1 pin. 101the output is nominally 13.5 mhz llc on the llc1 pin. table 98. p15Cp0 outp ut/input pin mapping data port pins p[15:0] format, and mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 video out, 8-bit, 4:2:2 ycrcb[7:0]out video out, 16-bit, 4:2:2 y[7:0]out crcb[7:0] out table 99. standard definition pixel port modes pixel port pins p[15: 0] of_sel[3:0] format p[15:8] p[7: 0] 0010 16-bit at llc2 4:2:2 y[7:0] crcb[7:0] 0011 (default) 8-bit at llc1 4:2:2 (default) yc rcb[7:0] (default) three-state 0110-1111 reserved reserved. do not use.
ADV7184 rev. 0 | page 72 of 108 mpu port description the ADV7184 supports a 2-wire (i 2 c-compatible) serial inter- face. two inputs, serial data (sda) and serial clock (sclk), carry information between the ADV7184 and the system i 2 c master controller. each slave device is recognized by a unique address. the ADV7184s i 2 c port allows the user to set up and configure the decoder and to read back captured vbi data. the ADV7184 has two possible slave addresses for both read and write operations, depending on the logic level on the alsb pin. these four unique addresses are shown in table 100. the alsb pin controls bit 1 of the slave address. by altering the alsb, it is possible to control two ADV7184s in an application without having a conflict with the same slave address. the lsb (bit 0) sets either a read or write operation. logic 1 corresponds to a read operation; logic 0 corresponds to a write operation. table 100. i 2 c address alsb r/w slave address 0 0 0x40 0 1 0x41 1 0 0x42 1 1 0x43 to control the device on the bus, a specific protocol must be followed. first, the master initiates a data transfer by establishing a start condition, which is defined by a high-to-low transition on sda while sclk remains high. this indicates that an address/data stream follows. all peripherals respond to the start condition and shift the next eight bits (7-bit address + r/w bit). the bits are transferred from msb down to lsb. the peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse; this is known as an acknowledge bit. all other devices withdraw from the bus at this point and maintain an idle condition. the idle condition is where the device monitors the sda and sclk lines, waiting for the start condition and the correct transmitted address. the r/w bit determines the direction of the data. logic 0 on the lsb of the first byte means the master writes information to the peripheral. logic 1 on the lsb of the first byte means the master reads information from the peripheral. the ADV7184 acts as a standard slave device on the bus. the data on the sda pin is eight bits long, supporting the 7-bit addresses plus the r/w bit. the ADV7184 has 249 subaddresses to enable access to the internal registers. it therefore interprets the first byte as the device address and the second byte as the starting subaddress. the subaddresses auto-increment, allowing data to be written to or read from the starting subaddress. a data transfer is always terminated by a stop condition. the user can also access any unique subaddress register on a one-by-one basis without updating all the registers. stop and start conditions can be detected at any stage during the data transfer. if these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. during a given sclk high period, the user should issue only one start condition, one stop condition, or a single stop condition followed by a single start condition. if an invalid subaddress is issued by the user, the ADV7184 does not issue an acknowledge and returns to the idle condition. if in autoincrement mode the highest subaddress is exceeded, the following action is taken: 1. in read mode, the highest subaddress register contents continue to be output until the master device issues a no acknowledge. this indicates the end of a read. in a no acknowledge condition the sda line is not pulled low on the ninth pulse. 2. in write mode, the data for the invalid byte is not loaded into any subaddress register, a no acknowledge is issued by the ADV7184, and the part returns to the idle condition. 05479-049 sdata sclock start addr ack ack data ack stop subaddress 1?7 1?7 89 8 9 1?789 s p r/w figure 44. bus data transfer 05479-050 s write s equence slave addr a(s) sub addr a(s) data a(s) data a(s) p s read s equence slave addr slave addr a(s) sub addr a(s) s a(s) data a(m) data a(m) p s = start bit p = stop bit a(s) = acknowledge by slave a(m) = acknowledge by master a(s) = no-acknowledge by slave a(m) = no-acknowledge by master lsb = 1 lsb = 0 figure 45. read and write sequence
ADV7184 rev. 0 | page 73 of 108 register accesses the mpu can write to or read from most of the ADV7184s registers, excepting the registers that are read only or write only. the subaddress register determines which register the next read or write operation accesses. all communications with the part through the bus start with an access to the subaddress register. a read/write operation is then performed from/to the target address, which then increments to the next address until a stop command on the bus is performed. register programming the i 2 c register maps section describes each register in terms of its configuration. after the part has been accessed over the bus and a read/write operation is selected, the subaddress is set up. the subaddress register determines to/from which register the operation takes place. table 103and table 104 list the various operations under the control of the subaddress register. as can be seen in figure 46, the registers in the ADV7184 are arranged into two maps: the user map (enabled by default) and the user sub map. the user sub map has controls for the interrupt and vdp functionality on the ADV7184 and the user map controls everything else. the user map and the user sub map consist of a common space from address 0x00 to 0x3f. depending on how bit 5 in register 0x0e (sub_usr_en) is set, the register map then splits in two sections. sub_usr_en, address 0x0e [5] this bit splits the register map at register 0x40. 0 (default)the register map does not split and the user map is enabled. 1the register map splits and the user sub map is enabled. common i 2 c space address 0x00 0x3f address 0x0e bit 5 = 0b address 0x0e bit 5 = 1b i 2 c space address 0x40 0xff i 2 c space address 0x40 0x9c user map user sub map normal register space interrupt and vdp register space 05479-048 figure 46: register access user map and user sub map i 2 c sequencer an i 2 c sequencer is used when a parameter exceeds eight bits, and is therefore distributed over two or more i 2 c registers, for example, hsb [11:0]. when such a parameter is changed using two or more i 2 c write operations, the parameter may hold an invalid value for the time between the first and last i 2 c being completed. in other words, the top bits of the parameter may already hold the new value while the remaining bits of the parameter still hold the previous value. to avoid this problem, the i 2 c sequencer holds the already updated bits of the parameter in local memory; all bits of the parameter are updated together once the last register write operation has completed. the correct operation of the i 2 c sequencer relies on the following: ? all i 2 c registers for the parameter in question must be written to in order of ascending addresses. for example, for hsb[10:0], write to address 0x34 first, followed by 0x35. ? no other i 2 c taking place between the two (or more) i 2 c writes for the sequence. for example, for hsb[10:0], write to address 0x34 first, immediately followed by 0x35.
ADV7184 rev. 0 | page 74 of 108 i 2 c register maps user map the collective name for the registers in table 101 below is the user map. table 101. user map register details address reset dec hex register name rw 7 6 5 4 3 2 1 0 value (hex) 0 00 input ctrl rw vid_sel.3 vid_sel.2 vid_sel. 1 vid_sel.0 insel.3 insel.2 insel.1 insel.0 00000000 00 1 01 video selection rw enhspll betacam envsproc 11001000 c8 3 03 output ctrl rw vbi_en tod of_sel.3 of_s el.2 of_sel.1 of_sel.0 sd_dup_av 00001100 0c 4 04 ext output ctrl rw bt656-4 tim_oe bl_c_vbi en_sfl_pin range 01xx0101 45 7 07 autodetect enable rw ad_sec525_en ad_secam_en ad_n443_en ad _p60_en ad_paln_en ad_palm_en ad_ntsc_en ad_pal_en 01111111 7f 8 08 contrast rw con.7 con.6 con.5 con.4 con.3 con.2 con.1 con.0 10000000 80 10 0a brightness rw bri.7 bri.6 bri.5 bri.4 bri.3 bri.2 bri.1 bri.0 00000000 00 11 0b hue rw hue.7 hue.6 hue.5 hu e.4 hue.3 hue.2 hue.1 hue.0 00000000 00 12 0c default value y rw def_y.5 def_ y.4 def_y.3 def_y.2 def_y.1 def_y.0 def_val_ auto_en def_val_en 00110110 36 13 0d default value c rw def_c. 7 def_c.6 def_c.5 def_ c.4 def_c.3 def_c.2 de f_c.1 def_c.0 01111100 7c 14 0e adi ctrl sub_usr_en 00000000 00 15 0f power mgmt rw res pwrdn pdbp fb_pwrdn 00000000 00 16 10 status 1 r col_kill ad_result.2 ad_result.1 ad_r esult.0 follow_pw fsc_lock lost_lock in_lock --- --- 18 12 status 2 r fsc nstd ll nstd mv agc det mv ps det mvcs t3 mvcs det --- --- 19 13 status 3 r pal_sw_lock interlace std fld len free_run_act cvbs sd_op_50hz gemd inst_hlock --- --- 19 13 analog ctrl internal w xtal_ttl_sel 00000000 00 20 14 analog clamp ctrl rw cclen 00010010 12 21 15 digital clamp ctrl 1 rw dct.1 dct.0 0000xxxx 00 23 17 shaping filter ctrl rw csfm.2 csfm.1 csfm .0 ysfm.4 ysfm.3 ysfm.2 ysfm.1 ysfm.0 00000001 01 24 18 shaping filter ctrl 2 rw wysfmovr wysfm.4 wysfm.3 wysfm.2 wysfm.1 wysfm.0 10010011 93 25 19 comb filter ctrl rw ns fsel.1 nsfsel.0 psfs el.1 psfsel.0 11110001 f1 29 1d adi ctrl 2 rw tri_llc en28xtal 00000xxx 00 39 27 pixel delay ctrl rw swpc auto_pdc_e n cta.2 cta.1 cta.0 lta.1 lta.0 01011000 58 43 2b misc gain ctrl rw cke pw_upd 11100001 e1 44 2c agc mode ctrl rw lagc.2 lagc .1 lagc.0 cagc.1 cagc.0 10101110 ae 45 2d chroma gain ctrl 1 w cagt.1 cagt .0 cmg.11 cmg.10 cmg.9 cmg.8 11110100 f4 46 2e chroma gain ctrl 2 w cmg.7 cmg.6 cmg.5 cmg.4 cmg.3 cmg.2 cmg.1 cmg.0 00000000 00 47 2f luma gain ctrl 1 w lagt.1 lgat.0 lmg.11 lmg.10 lmg.9 lmg.8 1111xxxx f0 48 30 luma gain ctrl 2 w lmg.7 lmg.6 lmg. 5 lmg.4 lmg.3 lmg.2 lmg.1 lmg.0 xxxxxxxx 00 49 31 vsync field ctrl 1 rw newavmode hvstim 00010010 12 50 32 vsync field ctrl 2 rw vsbho vsbhe 01000001 41 51 33 vsync field ctrl 3 rw vseho vsehe 10000100 84 52 34 hsync pos ctrl 1 rw hsb.10 hsb.9 hsb.8 hse.10 hse.9 hse.8 00000000 00 53 35 hsync pos ctrl 2 rw hsb.7 hsb.6 hs b.5 hsb.4 hsb.3 hsb.2 hsb.1 hsb.0 00000010 02 54 36 hsync pos ctrl 3 rw hse.7 hse.6 hs e.5 hse.4 hse.3 hse.2 hse.1 hse.0 00000000 00 55 37 polarity rw phs pvs pf pclk 00000001 01 56 38 ntsc comb ctrl rw ctapsn.1 ctapsn.0 ccmn.2 ccmn.1 ccmn.0 ycmn.2 ycmn.1 ycmn.0 10000000 80 57 39 pal comb ctrl rw ctapsp.1 ctapsp.0 ccm p.2 ccmp.1 ccmp.0 ycmp.2 ycmp.1 ycmp.0 11000000 c0 58 3a adc ctrl rw pdn_adc0 pdn_adc1 pdn_adc2 pdn_adc3 00010001 11 61 3d man window ctrl rw ckillthr.2 ckillthr.1 ckillthr.0 01000011 43 65 41 resample ctrl rw sfl_inv 00000001 01 72 48 gemstar ctrl 1 rw gdecel.15 gdecel.14 gdecel.13 gdecel.12 gdecel.11 gdecel.10 gdecel.9 gdecel.8 00000000 00 73 49 gemstar ctrl 2 rw gdecel.7 gdecel.6 gdecel.5 gdecel.4 gdecel.3 gdecel.2 gdecel.1 gdecel.0 00000000 00 74 4a gemstar ctrl 3 rw gdecol.15 gdecol.14 gdecol.13 gdecol.12 gdecol.11 gdecol.10 gdecol.9 gdecol.8 00000000 00 75 4b gemstar ctrl 4 rw gdecol.7 gdecol.6 gdecol.5 gdecol.4 gdecol.3 gdecol.2 gdecol.1 gdecol.0 00000000 00 76 4c gemstar ctrl 5 rw gdecad xxxx0000 00 77 4d cti dnr ctrl 1 rw dnr_en cti_ab.1 cti_ab.0 ct i_ab_en cti_en 11101111 ef 78 4e cti dnr ctrl 2 rw cti_c_th.7 cti_c_th.6 cti_c_th.5 ct i_c_th.4 cti_c_th.3 cti_c_th.2 cti_c_th.1 cti_c_th.0 00001000 08 80 50 cti dnr ctrl 4 rw dnr_th.7 dnr_th.6 dnr_th.5 dnr_th.4 dnr_th.3 dnr_th.2 dnr_th.1 dnr_th.0 00001000 08 81 51 lock count rw fscle srls col.2 col.1 col.0 cil.2 cil.1 cil.0 00100100 24 143 8f free run line length1 w llc_pad_ sel_man llc_pad_ sel.1 llc_pad_ sel.0 00000000 00 153 99 ccap 1 r ccap1.7 ccap1.6 ccap1.5 ccap1 .4 ccap1.3 ccap1.2 ccap1.1 ccap1.0 --- --- 154 9a ccap 2 r ccap2.7 ccap2.6 ccap2.5 ccap2 .4 ccap2.3 ccap2.2 ccap2.1 ccap2.0 --- ---
ADV7184 rev. 0 | page 75 of 108 address reset dec hex register name rw 7 6 5 4 3 2 1 0 value (hex) 155 9b letterbox 1 r lb_lct .7 lb_lct.6 lb_lct.5 lb _lct.4 lb_lct.3 lb_lct.2 lb_lct.1 lb_lct.0 --- --- 156 9c letterbox 2 r lb_lcm .7 lb_lcm.6 lb_lcm.5 lb _lcm.4 lb_lcm.3 lb_lcm.2 lb_lcm.1 lb_lcm.0 --- --- 157 9d letterbox 3 r lb_lcb .7 lb_lcb.6 lb_lcb.5 lb _lcb.4 lb_lcb.3 lb_lcb.2 lb_lcb.1 lb_lcb.0 --- --- 195 c3 adc switch 1 rw adc1_sw.3 adc1_sw.2 adc1_sw.1 adc1 _sw.0 adc0_sw.3 adc0_sw.2 adc0_sw.1 adc0_sw.0 xxxxxxxx 00 196 c4 adc switch 2 rw adc_sw_man adc2_sw.3 adc2_sw.2 adc2_sw.1 adc2_sw.0 0xxxxxxx 00 220 dc letterbox ctrl1 rw lb_t h.4 lb_th.3 lb_th.2 lb_th.1 lb_th.0 10101100 ac 221 dd letterbox ctrl2 rw lb_sl.3 lb_sl.2 lb_sl.1 lb_sl.0 lb_el.3 lb_el.2 lb_el.1 lb_el.0 01001100 4c 222 de st noise readback 1 r st_n oise_vld st_noise.10 st_noise.9 st_noise.8 --- --- 223 df st noise readback 2 r st_noise.7 st_noise.6 st_noise.5 st_noise.4 st_noise.3 st_noise.2 st_noise.1 st_noise.0 --- --- 225 e1 sd offset cb rw sd_off_cb.7 sd_off_cb.6 sd_off_cb.5 sd_off_cb.4 sd_off_cb.3 sd_off_cb .2 sd_off_cb.1 sd_off_cb.0 10000000 80 226 e2 sd offset cr rw sd_off_cr.7 sd_o ff_cr.6 sd_off_cr.5 sd_off_cr.4 sd_off_cr.3 sd_off_cr.2 sd_off_cr.1 sd_off_cr.0 10000000 80 227 e3 sd saturation cb rw sd_sat_cb.7 sd_sat_cb.6 sd_sat_cb. 5 sd_sat_cb.4 sd_sat_cb.3 sd_sat _cb.2 sd_sat_cb.1 sd_sat_cb.0 1000 0000 80 228 e4 sd saturation cr rw sd_sat_cr.7 sd_sat_cr.6 sd_sat_cr. 5 sd_sat_cr.4 sd_sat_cr.3 sd_sat _cr.2 sd_sat_cr.1 sd_sat_cr.0 1000 0000 80 229 e5 ntsc v bit begin rw nvbegd elo nvbegdele nvbegsign nvbeg.4 nv beg.3 nvbeg.2 nvbeg.1 nvbeg.0 00100101 25 230 e6 ntsc v bit end rw nvenddelo nvenddele nven dsign nvend.4 nvend.3 nven d.2 nvend.1 nvend.0 00000100 04 231 e7 ntsc f bit toggle rw nftogd elo nftogdele nftogsign nftog.4 nf tog.3 nftog.2 nftog.1 nftog.0 01100011 63 232 e8 pal v bit begin rw pvbegdelo pvbegdele pvbe gsign pvbeg.4 pvbeg.3 pvbe g.2 pvbeg.1 pvbeg.0 01100101 65 233 e9 pal v bit end rw pvenddelo pvenddele pvends ign pvend.4 pvend.3 pvend.2 pvend.1 pvend.0 00010100 14 234 ea pal f bit toggle rw pftogdelo pftogdele pfto gsign pftog.4 pftog.3 pfto g.2 pftog.1 pftog.0 01100011 63 235 eb vblank ctrl 1 rw nvbiolcm.1 nvbiolcm.0 nvbielcm.1 nv bielcm.0 pvbiolcm.1 pvbiolcm.0 pvbielcm.1 pvbielcm.0 01010101 55 236 ec vblank ctrl2 rw nvbioccm.1 nvbio ccm.0 nvbieccm.1 nvbieccm.0 pvbioccm.1 pvbioccm.0 pvbieccm.1 pvbieccm.0 01010101 55 237 ed fb_status r fb_status.3 fb_status.2 fb_status.1 fb_status.0 --- --- 237 ed fb_control1 w fb_inv cvbs_rgb_sel fb_mode.1 fb_mode.0 00010000 10 238 ee fb_control 2 rw fb_csc_man man_alpha_ val.6 man_alpha_ val.5 man_alpha_ val.4 man_alpha_ val.3 man_alpha_ val.2 man_alpha_ val.1 man_alpha_ val.0 00000000 00 239 ef fb_control 3 rw fb_sp_ adjust.3 fb_sp_ adjust.2 fb_sp_ adjust.1 fb_sp_ adjust.0 cntr_ enable fb_edge_ shape..2 fb_edge_ shape.1 fb_edge_ shape.0 01001010 4a 240 f0 fb_control 4 rw fb_del ay.3 fb_delay.2 fb_delay.1 fb_delay.0 01000100 44 241 f1 fb_control 5 rw cntr_level.1 cntr _level.0 fb_level.1 fb_level.0 cntr_mode.1 cntr_ mode.0 rgb_ip_sel 00001100 0c 243 f3 afe_control 1 rw adc3_sw.3 adc3_sw.2 adc3_sw.1 adc3 _sw.0 aa_filt_en.3 aa_filt_en.2 aa_filt_en.1 aa_filt_en.0 00000000 00 244 f4 drive strength rw dr_str dr_str.0 dr_str_c dr_str_c.0 dr_s tr_s dr_str_s.0 xx010101 15 248 f8 if comp ctrl rw iffiltsel.2 iffiltsel.1 iffiltsel.0 00000000 00 249 f9 vs mode ctrl rw vs_coast_ mode.1 vs_coast_ mode.0 extend_vs_ min_freq extend_vs_ max_freq 00000000 00 251 fb peaking ctrl rw peaking_ gain.7 peaking_ gain.6 peaking_ gain.5 peaking_ gain.4 peaking_ gain.3 peaking_ gain.2 peaking_ gain.1 peaking_ gain.0 01000000 40 252 fc coring threshold 2 rw dnr_th2.7 dnr_th2.6 dnr_th2. 5 dnr_th2.4 dnr_th2.3 dnr_th 2.2 dnr_th2.1 dnr_th2.0 00000100 04
ADV7184 rev. 0 | page 76 of 108 table 102 provides a detailed description of the registers located in the user map. table 102. user map detailed description bit address register bit description 7 6 5 4 3 2 1 0 comments notes 0 0 0 0 cvbs in on ain1, scart: g on ain6/ain9, b on ain4/ain7, r on ain5/ain8 0 0 0 1 cvbs in on ain2, scart: g on ain6/ain9, b on ain4/ain7, r on ain5/ain8 0 0 1 0 cvbs in on ain3, scart: g on ain6/ain9, b on ain4/ain7, r on ain5/ain8 0 0 1 1 cvbs in on ain4, scart: g on ain9, b on ain7, r on ain8 0 1 0 0 cvbs in on ain5, scart: g on ain9, b on ain7, r on ain8 0 1 0 1 cvbs in on ain6, scart: g on ain9, b on ain7, r on ain8 composite and scart rgb (rgb analog input options selectable via rgb_ip_sel) 0 1 1 0 y on ain1, c on ain4 0 1 1 1 y on ain2, c on ain5 1 0 0 0 y on ain3, c on ain6 s-video 1 0 0 1 y on ain1, pb on ain4, pr on ain5 1 0 1 0 y on ain2, pb on ain3, pr on ain6 ypbpr 1 0 1 1 cvbs in on ain7, scart: g on ain6, b on ain4, r on ain5 1 1 0 0 cvbs in on ain8, scart: g on ain6, b on ain4, r on ain5 1 1 0 1 cvbs in on ain9, scart: g on ain6, b on ain4, r on ain5 1 1 1 0 cvbs in on ain10, scart: g on ain6/ain9, b on ain4/ain7, r on ain5/ain8 insel [3:0]. the insel bits allow the user to select an input channel as well as the input format. 1 1 1 1 cvbs in on ain11, scart: g on ain6/ain9, b on ain4/ain7, r on ain5/ain8 composite and scart rgb (rgb analog input options selectable via rgb_ip_sel) 0 0 0 0 auto-detect pal (bghid), ntsc (without pedestal), secam 0 0 0 1 auto-detect pal (bghid), ntsc (m) (with pedestal), secam 0 0 1 0 auto-detect pal (n), ntsc (m) (without pedestal), secam 0 0 1 1 auto-detect pal (n), ntsc (m) (with pedestal), secam 0 1 0 0 ntsc(j) 0x00 input control vid_sel [7:3]. the vid_sel bits allow the user to select the input video standard. 0 1 0 1 ntsc(m) 0 1 1 0 pal 60 0 1 1 1 ntsc 4.43 1000 pal bghid 1 0 0 1 pal n (bghid without pedestal) 1 0 1 0 pal m (without pedestal) 1011 pal m 1 1 0 0 pal combination n 1 1 0 1 pal combination n 1 1 1 0 secam (with pedestal) 1 1 1 1 secam (with pedestal) reserved. 0 0 0 set to default 0 disable vsync processor envsproc 1 enable vsync processor reserved. 0 set to default 0 standard video input betacam 1 betacam input enable 0 disable hsync processor enhspll 1 enable hsync processor 0x01 video selection reserved. 1 set to default
ADV7184 rev. 0 | page 77 of 108 bit address register bit description 7 6 5 4 3 2 1 0 comments notes 0 av codes to suit 8-bit interleaved data output sd_dup_av. duplicates the av codes from the luma into the chroma path. 1 av codes duplicated (for 16-bit interfaces) reserved. 0 set as default 0 0 0 0 reserved 0 0 0 1 reserved 0 0 1 0 16-bit @ llc1 4:2:2 0 0 1 1 8-bit @ llc1 4:2:2 itu-r bt.656 0 1 0 0 not used 0 1 0 1 not used 0 1 1 0 not used 0 1 1 1 not used 1 0 0 0 not used 1 0 0 1 not used 1 0 1 0 not used 1 0 1 1 not used 1 1 0 0 not used 1 1 0 1 not used 1 1 1 0 not used of_sel [3:0]. allows the user to choose from a set of output formats. 1 1 1 1 not used 0 output pins enabled tod. three-state output drivers. this bit allows the user to three-state the output drivers: p[19:0], hs, vs, field, and sfl. 1 drivers three-stated see also tim_oe and tri_llc 0 all lines filtered and scaled 0x03 output control vbi_en. allows vbi data (lines 1 to 21) to be passed through with only a minimum amount of filtering performed. 1 only active video region filtered 0 16 < y < 235, 16 < c < 240 itu-r bt.656 range. allows the user to select the range of output values. can be bt656 compliant, or can fill the whole accessible number range. 1 1 < y < 254, 1 < c < 254 extended range 0 sfl output is disabled en_sfl_pin 1 sfl information output on the sfl pin sfl output enables connecting encoder and decoder directly 0 decode and output color bl_c_vbi. blank chroma during vbi. if set, enables data in the vbi region to be passed through the decoder undistorted. 1 blank cr and cb during vbi 0 hs, vs, f three-stated tim_oe. timing signals output enable. 1 hs, vs, f forced active controlled by tod reserved. x x reserved. 1 0 bt656-3-complatible 0x04 extended output control bt656-4. allows the user to select an output mode-compatible with itu- r bt656-3/4. 1 bt656-4-compatible 0 disable ad_pal_en. pal b/g/i/h autodetect enable. 1 enable 0 disable ad_ntsc_en. ntsc autodetect enable. 1 enable 0 disable ad_palm_en. pal m autodetect enable. 1 enable 0 disable ad_paln_en. pal n autodetect enable. 1 enable 0 disable ad_p60_en. pal 60 autodetect enable. 1 enable 0 disable ad_n443_en. ntsc443 autodetect enable. 1 enable 0 disable ad_secam_en. secam autodetect enable. 1 enable 0 disable 0x07 autodetect enable ad_sec525_en. secam 525 autodetect enable. 1 enable 0x08 contrast register con[7:0]. contrast adjust. this is the user control for contrast adjustment. 1 0 0 0 0 0 0 0 luma gain = 1 0x00 gain = 0; 0x80 gain = 1; 0xff gain = 2 0x09 reserved. reserved. 1 0 0 0 0 0 0 0
ADV7184 rev. 0 | page 78 of 108 bit address register bit description 7 6 5 4 3 2 1 0 comments notes 0x0a brightness register bri[7:0]. this register controls the brightness of the video signal. 0 0 0 0 0 0 0 0 0x00 = 0mv 0x7f = +204mv 0x80 = -204mv 0x0b hue register hue[7:0]. this register contains the value for the color hue adjustment. 0 0 0 0 0 0 0 0 hue range =C90 to +90 0 free-run mode dependent on def_val_auto_en def_val_en. default value enable. 1 force free-run mode on and output blue screen 0 disable free-run mode def_val_auto_en. default value. 1 enable automatic free-run mode (blue screen) when lock is lost, free-run mode can be enabled to output stable timing, clock, and a set color. 0 0 1 1 0 1 0x0c default value y def_y[5:0]. default value y. this register holds the y default value. y[7:0] = {def_y[5:0],0, 0} default y value output in free- run mode. 0 1 1 1 1 1 0 0 0x0d default value c def_c[7:0]. default value c. the cr and cb default values are defined in this register. cr[7:0] = def_c[7:4],0, 0, 0, 0} cb[7:0] = def_c[3:0], 0, 0, 0, 0} default cb/cr value output in free-run mode. default values give blue screen output. reserved.. 0 0 0 0 0 set as default 0 access user map sub_usr_en. enables the user to access the user sub map 1 access user sub map see figure 46. 0x0e adi control reserved. 0 0 set as default reserved. 0 set to default 0 fb input operational fb_pwrdn 1 fb input in power save mode 0 chip power-down controlled by pin pdbp. power-down bit priority selects between pwrdn bit or pin. 1 bit has priority (pin disregarded) reserved. 0 0 set to default 0 system functional pwrdn. power-down places the decoder in a full power-down mode. 1 powered down see pdbp, 0x0f bit 2. reserved. 0 set to default 0 normal operation 0x0f power management res. chip reset loads all i 2 c bits with default values. 1 start reset sequence executing reset takes approx. 2 ms. self-clearing. in_lock x in lock (right now) = 1 lost_lock x lost lock (since last read) = 1 fsc_lock x fsc lock (right now) = 1 follow_pw x peak white agc mode active = 1 provides information about the internal status of the decoder. 000 ntsm-mj 0 0 1 ntsc-443 010 pal-m 0 1 1 pal-60 100 pal-bghid 101 secam 1 1 0 pal combination n ad_result[2:0]. autodetection result reports the standard of the input video. 1 1 1 secam 525 detected standard 0x10 status register 1 (read only) col_kill x color kill is active = 1 color kill mvcs det x mv color striping detected 1 = detected mvcs t3 x mv color striping type 0 = type 2; 1 = type 3 mv_ps det x mv pseudo sync detected 1 = detected mv_agc det x mv agc pulses detected 1 = detected ll_nstd x nonstandard line length 1 = detected fsc_nstd x fsc frequency nonstandard 1 = detected 0x12 status register 2 (read only) reserved. x x inst_hlock x 1 = horizontal lock achieved unfiltered gemd x 1 = gemstar data detected when gemd bit goes high, it will remain high until end of active video lines in that field. sd_op_50hz x sd field rate detect 0 = sd 60 hz detected; 1 = sd 50 hz detected. cvbs x result of cvbs /yc autodetection 0 = y/c; 1 = cvbs free_run_act x 1 = free-run mode active blue screen output std fld_len x 1 = field length standard correct field length found 0x13 status register 3 (read only) interlaced x 1 = interlaced video detected field sequence found
ADV7184 rev. 0 | page 79 of 108 bit address register bit description 7 6 5 4 3 2 1 0 comments notes pal_sw_lock x 1 = swinging burst detected reliable swinging burst sequence reserved. 0 0 0 crystal used to derive 28.63636 mhz clock xtal_ttl_sel 1 external ttl level clock supplied 0x13 analogue control internal (write only) reserved. 0 0 0 0 0 reserved. 0 0 1 0 set to default 0 current sources switched off cclen. current clamp enable allows the user to switch off the current sources in the analog front. 1 current sources enabled 0x14 analog clamp control reserved. 0 0 0 set to default reserved. 0 x x x x set to default 0 0 slow (tc = 1 sec) 0 1 medium (tc = 0.5 sec) 1 0 fast (tc = 0.1 sec) dct[1:0]. digital clamp timing determines the time constant of the digital fine clamp circuitry. 1 1 tc dependent on video 0x15 digital clamp control 1 reserved. 0 set to default 0 0 0 0 0 auto wide notch for poor quality sources or wide-band filter with comb for good quality input 0 0 0 0 1 auto narrow notch for poor quality sources or wideband filter with comb for good quality input decoder selects optimum y- shaping filter depending on cvbs quality. 0 0 0 1 0 svhs 1 0 0 0 1 1 svhs 2 0 0 1 0 0 svhs 3 0 0 1 0 1 svhs 4 0 0 1 1 0 svhs 5 0 0 1 1 1 svhs 6 0 1 0 0 0 svhs 7 0 1 0 0 1 svhs 8 0 1 0 1 0 svhs 9 0 1 0 1 1 svhs 10 0 1 1 0 0 svhs 11 0 1 1 0 1 svhs 12 0 1 1 1 0 svhs 13 0 1 1 1 1 svhs 14 1 0 0 0 0 svhs 15 1 0 0 0 1 svhs 16 1 0 0 1 0 svhs 17 0x17 shaping filter control 1 0 0 1 1 svhs 18 (ccir601) 1 0 1 0 0 pal nn1 1 0 1 0 1 pal nn2 1 0 1 1 0 pal nn3 1 0 1 1 1 pal wn 1 1 1 0 0 0 pal wn 2 1 1 0 0 1 ntsc nn1 1 1 0 1 0 ntsc nn2 1 1 0 1 1 ntsc nn3 1 1 1 0 0 ntsc wn1 1 1 1 0 1 ntsc wn2 1 1 1 1 0 ntsc wn3 ysfm[4:0]. selects y-shaping filter mode when in cvbs only mode. allows the user to select a wide range of low-pass and notch filters. if either auto mode is selected, the decoder selects the optimum y filter depending on the cvbs video source quality (good vs. bad). 1 1 1 1 1 reserved if one of these modes is selected, the decoder does not change filter modes. depending on video quality, a fixed filter response (the one selected) is used for good and bad quality video. 0x17 shaping filter control 0 0 0 auto selection 15 mhz (cont.) 0 0 1 auto selection 2.17 mhz automatically selects a c filter based on video standard and quality. 010 sh1 011 sh2 100 sh3 101 sh4 110 sh5 csfm[2:0]. c-shaping filter mode allows the selection from a range of low-pass chrominance filters. if either auto mode is selected, the decoder selects the optimum c filter depending on the cvbs video source quality (good vs. bad). non-auto settings force a c filter for all standards and quality of cvbs video. 1 1 1 wideband mode selects a c filter for all video standards and for good and bad video. 0 0 0 0 0 reserved. do not use. 0 0 0 0 1 reserved. do not use. 0x18 shaping filter control 2 wysfm[4:0]. wideband y-shaping filter mode allows the user to select which y shaping filter is used for the y component 0 0 0 1 0 svhs 1
ADV7184 rev. 0 | page 80 of 108 bit address register bit description 7 6 5 4 3 2 1 0 comments notes 0 0 0 1 1 svhs 2 0 0 1 0 0 svhs 3 0 0 1 0 1 svhs 4 0 0 1 1 0 svhs 5 0 0 1 1 1 svhs 6 0 1 0 0 0 svhs 7 0 1 0 0 1 svhs 8 0 1 0 1 0 svhs 9 0 1 0 1 1 svhs 10 0 1 1 0 0 svhs 11 0 1 1 0 1 svhs 12 0 1 1 1 0 svhs 13 0 1 1 1 1 svhs 14 1 0 0 0 0 svhs 15 1 0 0 0 1 svhs 16 1 0 0 1 0 svhs 17 1 0 0 1 1 svhs 18 (ccir 601) 1 0 1 0 0 reserved. do not use. ~ ~ ~ ~ ~ reserved. do not use. of y/c, ypbpr, b/w input signals; it is also used when a good quality input cvbs signal is detected. for all other inputs, the y- shaping filter chosen is controlled by ysfm[4:0]. 1 1 1 1 1 reserved. do not use. reserved. 0 0 set to default 0 auto selection of best filter wysfmovr. enables the use of automatic wysfn filter. 1 manual select filter using wysfm[4:0] 0 0 narrow 0 1 medium 1 0 wide psfsel[1:0]. controls the signal bandwidth that is fed to the comb filters (pal). 1 1 widest 0 0 narrow 0 1 medium 1 0 medium nsfsel[1:0]. controls the signal bandwidth that is fed to the comb filters (ntsc). 1 1 wide 0x19 comb filter control reserved. 1 1 1 1 set as default reserved. 0 0 0 x x x set to default 0 use 27 mhz crystal en28xtal 1 use 28..63636 mhz crystal 0 llc pin active 0x1d adi control 2 tri_llc 1 llc pin three-stated 0 0 no delay 1 0 luma 1 clk (37 ns) delayed 1 0 luma 2 clk (74 ns) early lta[1:0]. luma timing adjust allows the user to specify a timing difference between chroma and luma samples. 1 1 luma 1 clk (37 ns) early cvbs mode lta[1:0] = 00b s-video mode lta[1:0]= 01b yprpb mode lta[1:0] = 01b reserved. 0 set to zero 0 0 0 not valid setting 0 0 1 chroma + 2 pixels (early) 0 1 0 chroma + 1 pixel (early) 0 1 1 no delay 1 0 0 chroma ? 1 pixel (late) 1 0 1 chroma ? 2 pixels (late) 1 1 0 chroma ? 3 pixels (late) cta[2:0]. chroma timing adjust allows a specified timing difference between the luma and chroma samples. 1 1 1 not valid setting cvbs mode cta[2:0] = 011b s-video mode cta[2:0] = 101b yprpb mode cta[2:0] = 110b 0 use values in lta[1:0] and cta[2:0] for delaying luma/chroma auto_pdc_en. automatically programs the lta/cta values to align luma and chroma at the output for all modes of operation. 1 lta and cta values determined automatically 0 no swapping 0x27 pixel delay control swpc. allows the cr and cb samples to be swapped. 1 swap the cr and cb o/p samples 0 update once per video line pw_upd. peak white update determines the rate of gain. 1 update once per field peak white must be enabled. see lagc[2:0] reserved. 1 0 0 0 0 set to default 0x2b misc gain control cke. color kill enable allows the color kill 0 color kill disabled for secam color kill, threshold
ADV7184 rev. 0 | page 81 of 108 bit address register bit description 7 6 5 4 3 2 1 0 comments notes function to be switched on and off. 1 color kill enabled is set at 8%. see ckillthr[2:0] reserved. 1 set to default 0 0 manual fixed gain use cmg[11:0] 0 1 use luma gain for chroma 1 0 automatic gain based on color burst cagc[1:0]. chroma automatic gain control selects the basic mode of operation for the agc in the chroma path. 1 1 freeze chroma gain reserved. 1 1 set to 1 0 0 0 manual fixed gain use lmg[11:0] 0 0 1 agc peak white algorithm off blank level to sync tip 0 1 0 agc peak white algorithm on blank level to sync tip 011 reserved 100 reserved 101 reserved 110 reserved lagc[2:0]. luma automatic gain control selects the mode of operation for the gain control in the luma path. 1 1 1 freeze gain 0x2c agc mode control reserved. 1 set to 1 cmg[11:8]. chroma manual gain can be used to program a desired manual chroma gain. reading back from this register in agc mode gives the current gain. 0 1 0 0 cagc[1:0] settings decide in which mode cmg[11:0] operates reserved. 1 1 set to 1 00 slow (tc = 2 s) 01 medium (tc = 1 s) 10 fast (tc = 0.2 s) 0x2d chroma gain control 1 cagt[1:0]. chroma automatic gain timing allows adjustment of the chroma agc tracking speed. 1 1 adaptive has an effect only if cagc[1:0] is set to auto gain (10) 0x2e chroma gain control 2 cmg[7:0 ]. chroma manual gain lower 8 bits. see cmg[11:8] for description. 0 0 0 0 0 0 0 0 cmg[11:0] = 750d; gain is 1 in ntsc cmg[11:0] = 741d; gain is 1 in pal min value is 0d (g = C60 db) max value is 3750 (g = 5) lmg[11:8]. luma manual gain can be used to program a desired manual chroma gain, or to read back the actual gain value used. x x x x lagc[1:0] settings decide in which mode lmg[11:0] operates reserved. 1 1 set to 1 00 slow (tc = 2 s) 01 medium (tc = 1 s) 10 fast (tc = 0.2 s) 0x2f luma gain control 1 lagt[1:0]. luma automatic gain timing allows adjustment of the luma agc tracking speed. 1 1 adaptive only has an effect if lagc[1:0] is set to auto gain (001, 010, 011,or 100) 0x30 luma gain control 2 lmg[7:0]. lu ma manual gain can be used to program a desired manual chroma gain or read back the actual used gain value. x x x x x x x x lmg[11:0] = 1128dec; gain is 1 in ntsc lmg[11:0] = 1222d; gain is 1 in pal min value ntsc 1024 (g = 0.90); pal (g = 0.84) max value ntsc 4095 (g = 3.63); pal (g = 3.35) reserved. 0 1 0 set to default 0 start of line relative to hse hse = hsync end hvstim. selects where within a line of video the vs signal is asserted. 1 start of line relative to hsb hsb = hsync begin 0 eav/sav codes generated to suit adi encoders newavmode. sets the eav/sav mode. 1 manual vs/field position controlled by registers 0x32, 0x33, and 0xe5C 0xea 0x31 vs and field control 1 reserved. 0 0 0 set to default reserved. 0 0 0 0 0 1 set to default 0 vs goes high in the middle of the line (even field) vsbhe 1 vs changes state at the start of the line (even field) 0 vs goes high in the middle of the line (odd field) 0x32 vsync field control 2 vsbho 1 vs changes state at the start of the line (odd field) newavmode bit must be set high. reserved. 0 0 0 1 0 0 set to default 0 vs goes low in the middle of the line (even field) 0x33 vsync field control 3 vsehe 1 vs changes state at the start of the line (even field) newavmode bit must be set high.
ADV7184 rev. 0 | page 82 of 108 bit address register bit description 7 6 5 4 3 2 1 0 comments notes 0 vs goes low in the middle of the line (odd field) vseho 1 vs changes state at the start of the line odd field hse[10:8]. hs end allows the positioning of the hs output within the video line. 0 0 0 hs output ends hse[10:0] pixels after the falling edge of hsync using hsb and hse the user can program the position and length of the output hsync reserved. 0 set to 0 hsb[10:8]. hs begin allows the positioning of the hs output within the video line. 0 0 0 hs output starts hsb[10:0] pixels after the falling edge of hsync 0x34 hs position control 1 reserved. 0 set to 0 0x35 hs position control 2 hsb[7:0]. see above, using hsb[10:0] and hse[10:0], the user can program the position and length of hs output signal. 0 0 0 0 0 0 1 0 0x36 hs position control 3 hse[7:0]. see above. 0 0 0 0 0 0 0 0 0 invert polarity pclk. sets the polarity of llc1. 1 normal polarity as per the timing diagrams reserved. 0 0 set to 0 0 active high pf. sets the field polarity. 1 active low reserved. 0 set to 0 0 active high pvs. sets the vs polarity. 1 active low reserved. 0 set to 0 0 active high 0x37 polarity phs. sets hs polarity. 1 active low 0 0 0 adaptive 3-line, 3-tap luma 1 0 0 use low-pass notch 1 0 1 fixed luma comb (2-line) top lines of memory 1 1 0 fixed luma comb (3-line) all lines of memory ycmn[2:0]. luma comb mode, ntsc. 1 1 1 fixed luma comb (2-line) bottom lines of memory 0 0 0 3-line adaptive for ctapsn = 01 4-line adaptive for ctapsn = 10 5-line adaptive for ctapsn = 11 100 disable chroma comb 1 0 1 fixed 2-line for ctapsn = 01 fixed 3-line for ctapsn = 10 fixed 4-line for ctapsn = 11 top lines of memory 1 1 0 fixed 3-line for ctapsn = 01 fixed 4-line for ctapsn = 10 fixed 5-line for ctapsn = 11 all lines of memory ccmn[2:0]. chroma comb mode, ntsc. 1 1 1 fixed 2-line for ctapsn = 01 fixed 3-line for ctapsn = 10 fixed 4-line for ctapsn = 11 bottom lines of memory 00 not used 0 1 adapts 3 lines C 2 lines 1 0 adapts 5 lines C 3 lines 0x38 ntsc comb control ctapsn[1:0]. chroma comb taps, ntsc. 1 1 adapts 5 lines C 4 lines 0 0 0 adaptive 5-line, 3-tap luma comb 1 0 0 use low-pass notch 1 1 0 fixed luma comb top lines of memory 1 1 0 fixed luma comb (5-line) all lines of memory ycmp[2:0]. luma comb mode, pal. 1 1 1 fixed luma comb (3-line) bottom lines of memory 0 0 0 3-line adaptive for ctapsp = 01 4-line adaptive for ctapsp = 10 5-line adaptive for ctapsp = 11 1 0 0 disable chroma comb 1 0 1 fixed 2-line for ctapsp = 01 fixed 3-line for ctapsp = 10 fixed 4-line for ctapsp = 11 top lines of memory 1 1 0 fixed 3-line for ctapsp = 01 fixed 4-line for ctapsp = 10 fixed 5-line for ctapsp = 11 all lines of memory 0x39 pal comb control ccmp[2:0]. chroma comb mode, pal. 1 1 1 fixed 2-line for ctapsp = 01 fixed 3-line for ctapsp = 10 fixed 4-line for ctapsp = 11 bottom lines of memory
ADV7184 rev. 0 | page 83 of 108 bit address register bit description 7 6 5 4 3 2 1 0 comments notes 00 not used 0 1 adapts 5-lines C 2 lines (2 taps) 1 0 adapts 5 lines C 3 lines (3 taps) ctapsp[1:0]. chroma comb taps, pal. 1 1 adapts 5 lines C 4 lines (4 taps) 0 adc3 normal operation pwrdn_adc_3. enables power-down of adc3. 1 power down adc3 0 adc2 normal operation pwrdn_adc_2. enables power-down of adc2. 1 power down adc2 0 adc1 normal operation pwrdn_adc_1. enables power-down of adc1. 1 power down adc1 0 adc0 normal operation pwrdn_adc_0. enables power-down of adc0. 1 power down adc0 0x3a adc control reserved. 0 0 0 1 set as default reserved. 0 0 1 1 set to default 0 0 0 kill at 0.5% 0 0 1 kill at 1.5% 0 1 0 kill at 2.5% 0 1 1 kill at 4% 1 0 0 kill at 8.5% 1 0 1 kill at 16% 1 1 0 kill at 32% ckillthr[2:0]. 111 reserved cke = 1 enables the color kill function and must be enabled for ckillthr[2:0] to take effect. 0x3d manual window control reserved. 0 set to default reserved. 0 0 0 0 0 1 set to default 0 sfl compatible with adv7190/adv7191/ adv7194 & adv73xx encoders sfl_inv. controls the behavior of the pal switch bit. 1 sfl compatible with adv717x encoders 0x41 resample control reserved. 0 set to default 0x48 gemstar control 1 gdecel[ 15:8]. see the comments column. 0 0 0 0 0 0 0 0 0x49 gemstar control 2 gdecel[7:0]. see above. 0 0 0 0 0 0 0 0 gdecel[15:0]. 16 individual enable bits that select the lines of video (even field lines 10C25) that the decoder checks for gemstar- compatible data. lsb = line 10; msb = line 25 default = do not check for gemstar-compatible data on any lines [10C25] in even fields 0x4a gemstar control 3 gdecol[ 15:8]. see the comments column. 0 0 0 0 0 0 0 0 0x4b gemstar control 4 gdecol[7:0]. see above. 0 0 0 0 0 0 0 0 gdecol[15:0]. 16 individual enable bits that select the lines of video (odd field lines 10C25) that the decoder checks for gemstar- compatible data. lsb = line 10; msb = line 25 default = do not check for gemstar-compatible data on any lines [10C25] in odd fields 0 split data into half byte to avoid 00/ff code. gdecad. controls the manner in which decoded gemstar data is inserted into the horizontal blanking period. 1 output in straight 8-bit format 0x4c gemstar control 5 reserved. x x x x 0 0 0 undefined 0 disable cti cti_en. cti enable 1 enable cti 0 disable cti alpha blender cti_ab_en. enables the mixing of the transient improved chroma with the original signal. 1 enable cti alpha blender 0 0 sharpest mixing 0 1 sharp mixing 1 0 smooth cti_ab[1:0]. controls the behavior of the alpha-blend circuitry. 1 1 smoothest reserved. 0 set to default 0 bypass the dnr block dnr_en. enable or bypass the dnr block. 1 enable the dnr block 0x4d cti dnr control 1 reserved. 1 1 set to default 0x4e cti dnr control 2 cti_cth[7:0]. specifies how big the amplitude step must be to be steepened by the cti block. 0 0 0 0 1 0 0 0 set to 0x04 for a/v input; set to 0x0a for tuner input 0x50 cti dnr control 4 dnr_th[7:0]. specifies the maximum edge that is interpreted as noise and is therefore blanked. 0 0 0 0 1 0 0 0 0 0 0 1 line of video 0x51 lock count cil[2:0]. count-into-lock determines the number of lines the system must remain in 0 0 1 2 lines of video
ADV7184 rev. 0 | page 84 of 108 bit address register bit description 7 6 5 4 3 2 1 0 comments notes 0 1 0 5 lines of video 0 1 1 10 lines of video 1 0 0 100 lines of video 1 0 1 500 lines of video 1 1 0 1000 lines of video lock before showing a locked status. 1 1 1 100000 lines of video 0 0 0 1 line of video 0 0 1 2 lines of video 0 1 0 5 lines of video 0 1 1 10 lines of video 1 0 0 100 lines of video 1 0 1 500 lines of video 1 1 0 1000 lines of video col[2:0]. count-out-of-lock determines the number of lines the system must remain out-of-lock before showing a lost-locked status. 1 1 1 100000 lines of video 0 over field with vertical info srls. select raw lock signal. selects the determination of the lock status. 1 line-to-line evaluation 0 lock status set only by horizontal lock fscle. fsc lock enable. 1 lock status set by horizontal lock and subcarrier lock. 0 0 insel selects analog i/p muxing 0 1 cvbs C ain11 1 0 s-video C y on ain10 and c on ain12 sdm_sel[1:0] 1 1 cvbs/s-video autodetect cvbs on ain11 y on ain11 c on ain12 0x69 config 1 reserved. 0 0 0 0 0 x reserved. 0 0 0 0 set to default 0 0 0 llc1 (nominal 27 mhz) selected out on llc1 pin llc_pad_sel [2:0]. enables manual selection of clock for llc1 pin. 1 0 1 llc2 (nominally 13.5 mhz) selected out on llc1 pin for 16-bit 4:2:2 out, of_sel[3:0 = 0010 0x8f free run line length 1 reserved. 0 set to default 0x99 ccap1 (read only) ccap1[7:0]. closed caption data register. x x x x x x x x ccap1[7] contains parity bit for byte 0 only for use with vbi system 2 0x9a ccap2 (read only) ccap2[7:0]. closed caption data register. x x x x x x x x ccap2[7] contains parity bit for byte 0 only for use with vbi system 2 0x9b letterbox 1 (read only) lb_lct[7:0]. letterbox data register. x x x x x x x x reports the number of black lines detected at the top of active video. 0x9c letterbox 2 (read only) lb_lcm[7:0]. letterbox data register. x x x x x x x x reports the number of black lines detected in the bottom half of active video if subtitles are detected. 0x9d letterbox 3 (read only) lb_lcb[7:0]. letterbox data register. x x x x x x x x reports the number of black lines detected at the bottom of active video. this feature examines the active video at the start and at the end of each field. it enables format detection even if the video is not accompanied by a cgms or wss sequence. 0 0 0 0 no connection 0 0 0 1 ain1 0 0 1 0 ain2 0 0 1 1 ain3 0 1 0 0 ain4 0 1 0 1 ain5 0 1 1 0 ain6 0 1 1 1 no connection 1 0 0 0 no connection 1 0 0 1 ain7 1 0 1 0 ain8 1 0 1 1 ain9 1 1 0 0 ain10 1 1 0 1 ain11 1 1 1 0 ain12 0xc3 adc switch 1 adc0_sw[3:0]. manual muxing control for adc0. 1 1 1 1 no connection setadc_sw_man_en = 1 0xc3 adc switch 1 adc1_sw[3:0]. manual muxing contro l for 0 0 0 0 no connection setadc_sw_man_en = 1
ADV7184 rev. 0 | page 85 of 108 bit address register bit description 7 6 5 4 3 2 1 0 comments notes 0 0 0 1 no connection 0 0 1 0 no connection 0011 ain3 0100 ain4 0101 ain5 0110 ain6 0 1 1 1 no connection 1 0 0 0 no connection 1 0 0 1 no connection 1 0 1 0 no connection 1011 ain9 1 1 0 0 ain10 1 1 0 1 ain11 1 1 1 0 ain12 (cont.) adc1. 1 1 1 1 no connection 0 0 0 0 no connection 0 0 0 1 no connection 0 0 1 0 ain2 0 0 1 1 no connection 0 1 0 0 no connection 0 1 0 1 ain5 0 1 1 0 ain6 0 1 1 1 no connection 1 0 0 0 no connection 1 0 0 1 no connection 1 0 1 0 ain8 1 0 1 1 no connection 1 1 0 0 no connection 1 1 0 1 ain11 1 1 1 0 ain12 adc2_sw[3:0]. manual muxing control for adc2. 1 1 1 1 no connection setadc_sw_man_en = 1 reserved. x x x 0 disable 0xc4 adc switch 2 adc_sw_man_en. enables manual setting of the input signal muxing. 1 enable lb_th [4:0]. sets the threshold value that determines if a line is black. 0 1 1 0 0 default threshold for the detection of black lines. 0xdc letterbox control 1 reserved. 1 0 1 set as default lb_el[3:0]. programs the end line of the activity window for lb detection (end of field). 1 1 0 0 lb detection ends with the last line of active video on a field, 1100b: 262/525. 0xdd letterbox control 2 lb_sl[3:0]. programs the start line of the activity window for lb detection (start of field). 0 1 0 0 letterbox detection aligned with the start of active video, 0100b: 23/286 ntsc. st_noise[10:0] sync tip noise measurement st_noise[10:8] x x x st_noise_vld x 1 = st_noise[10:0] measurement valid 0 = st_noise[10:0] measurement invalid 0xde st noise readback 1 (read only) reserved. x x x x 0xdf st noise readback 2 (read only) st_noise[7:0] see st_noise[10:0] above x x x x x x x x 0xe1 sd offset cb sd_off_cb [7:0]. adjusts the hue by selecting the offset for the cb channel. 1 0 0 0 0 0 0 0 0xe2 sd offset cr sd_off_cr [7:0]. adjusts the hue by selecting the offset for the cr channel. 1 0 0 0 0 0 0 0 0xe3 sd saturation cb sd_sat_cb [7:0]. adjusts the saturation of the picture by affecting gain on the cb channel. 1 0 0 0 0 0 0 0 chroma gain = 0 db 0xe4 sd saturation cr sd_sat_cr [7:0]. adjusts the saturation of the picture by affecting gain on the cr channel. 1 0 0 0 0 0 0 0 chroma gain = 0 db 0xe5 ntsc v bit begin nvbeg[ 4:0]. how many lines after l count rollover to set v high. 0 0 1 0 1 ntsc default (bt.656)
ADV7184 rev. 0 | page 86 of 108 bit address register bit description 7 6 5 4 3 2 1 0 comments notes 0 set to low when manual programming nvbegsign 1 not suitable for user programming 0 no delay nvbegdele. delay v bit going high by one line relative to nvbeg (even field). 1 additional delay by 1 line 0 no delay nvbegdelo. delay v bit going high by one line relative to nvbeg (odd field). 1 additional delay by 1 line nvend[4:0]. how many lines after l count rollover to set v low. 0 0 1 0 0 ntsc default (bt.656) 0 set to low when manual programming nvendsign 1 not suitable for user programming 0 no delay nvenddele. delay v bit going low by one line relative to nvend (even field). 1 additional delay by 1 line 0 no delay 0xe6 ntsc v bit end nvenddelo. delay v bit going low by one line relative to nvend (odd field). 1 additional delay by 1 line nftog[4:0]. how many lines after l count rollover to toggle f signal. 0 0 0 1 1 ntsc default 0 set to low when manual programming nftogsign 1 not suitable for user programming 0 no delay nftogdele. delay f transition by one line relative to nftog (even field). 1 additional delay by 1 line 0 no delay 0xe7 ntsc f bit toggle nftogdelo. delay f transition by one line relative to nftog (odd field). 1 additional delay by 1 line pvbeg[4:0]. how many lines after l count rollover to set v high. 0 0 1 0 1 pal default (bt.656) 0 set to low when manual programming pvbegsign 1 not suitable for user programming 0 no delay pvbegdele. delay v bit going high by one line relative to pvbeg (even field). 1 additional delay by 1 line 0 no delay 0xe8 pal v bit begin pvbegdelo. delay v bit going high by one line relative to pvbeg (odd field). 1 additional delay by 1 line pvend[4:0]. how many lines after l count rollover to set v low. 1 0 1 0 0 pal default (bt.656) 0 set to low when manual programming pvendsign 1 not suitable for user programming 0 no delay pvenddele. delay v bit going low by one line relative to pvend (even field). 1 additional delay by 1 line 0 no delay 0xe9 pal v bit end pvenddelo. delay v bit going low by one line relative to pvend (odd field). 1 additional delay by 1 line pftog[4:0]. how many lines after l count rollover to toggle f signal. 0 0 0 1 1 pal default (bt.656) 0 set to low when manual programming pftogsign 1 not suitable for user programming 0 no delay pftogdele. delay f transition by one line relative to pftog (even field). 1 additional delay by 1 line 0 no delay 0xea pal f bit toggle pftogdelo. delay f transition by one line relative to pftog (odd field). 1 additional delay by 1 line 0 0 vbi ends 1 line earlier (line 335) 0 1 itu-r bt.470 compliant (line 336) 1 0 vbi ends 1 line later (line 337) pvbielcm[1:0]. pal vbi even field line control. 1 1 vbi ends 2 lines later (line 338) controls position of first active (comb filtered) line after vbi on even field in pal 0 0 vbi ends 1 line earlier (line 22) 0 1 itu-r bt.470 compliant (line 23) 1 0 vbi ends 1 line later (line 24) 0xeb v blank control 1 pvbiolcm[1:0]. pal vbi odd field line control. 1 1 vbi ends 2 lines later (line 25) controls position of first active (comb filtered) line after vbi on odd field in pal 0 0 vbi ends 1 line earlier (line 282) 0 1 itu-r bt.470 compliant (line 283) nvbielcm[1:0]. ntsc vbi even field line control. 1 0 vbi ends 1 line later (line 284) controls position of first active (comb filtered) line after vbi on even field in ntsc
ADV7184 rev. 0 | page 87 of 108 bit address register bit description 7 6 5 4 3 2 1 0 comments notes 1 1 vbi ends 2 lines later (line 285) 0 0 vbi ends 1 line earlier (line 20) 0 1 itu-r bt.470 compliant (line 21) 1 0 vbi ends 1 line later (line 22) pvbiolcm[1:0]. ntsc vbi odd field line control. 1 1 vbi ends 2 lines later (line 23) controls position of first active (comb filtered) line after vbi on odd field in ntsc 0 0 color output beginning line 335 0 1 itu-r bt.470 compliant color output beginning line 336 1 0 color output beginning line 337 pvbieccm[1:0]. pal vbi even field color control. 1 1 color output beginning line 338 controls the position of first line that outputs color after vbi on even field in pal 0 0 color output beginning line 22 0 1 itu-r bt.470 compliant color output beginning line 23 1 0 color output beginning line 24 pvbioccm[1:0]. pal vbi odd field color control. 1 1 color output beginning line 25 controls the position of first line that outputs color after vbi on odd field in pal 0 0 color output beginning line 282 0 1 itu-r bt.470 compliant color output beginning line 283 1 0 vbi ends 1 line later (line 284) nvbieccm[1:0]. ntsc vbi even field color control. 1 1 color output beginning line 285 controls the position of first line that outputs color after vbi on even field in ntsc 0 0 color output beginning line 20 0 1 itu-r bt.470 compliant color output beginning line 21 1 0 color output beginning line 22 0xec v blank control 2 nvbioccm[1:0]. ntsc vbi odd field color control. 1 1 color output beginning line 23 controls the position of first line that outputs color after vbi on odd field in ntsc 0xed fb_status (read only) reserved. x x x x fb_status[3:0]. provides information about the status of the fb pin. fb_status.0 x fb_rise, 1 = there has been a rising edge on fb pin since last i 2 c read self-clearing bit fb_status.1 x fb_fall, 1 = there has been a falling edge on fb pin since last i 2 c read self-clearing bit fb_status.2 x fb_stat, instantaneous value of fb signal at time of i 2 c read fb_status.3 x fb_high, indicates that the fb signal has gone high since the last i 2 c read self-clearing bit 0 0 static switch mode C full rgb or full cvbs data 0 1 fixed alpha blending, see man_alpha_val[6:0] 1 0 dynamic switching (fast mux) 1 1 dynamic switching with edge enhancement 0 cvbs source 1 rgb source selects either cvbs or rgb to be o/p 0 fb pin active high 1 fb pin active low 0xed fb_control 1 (write only) fb_mode[1:0]. selects fb mode. 0 0 0 1 man_alpha_val[6:0]. determines in what proportion the video from the cvbs source and the rgb source are blended. 0 0 0 0 0 0 0 0 automatic configuration of the csc for scart support 0xee fb_control 2 fb_csc_man 1 enable manual programming of csc csc is used to convert rgb portion of scart signal to ycrcb 0 0 0 0 0 1 0 1 0 0 1 1 fb_edge_shape[2:0] 1 0 0 improves picture transition for high speed fast blank switching 0xef fb_control 3 cntr_enable 0 contra st reduction mode disabled C fb signal interpreted as bi-level signal
ADV7184 rev. 0 | page 88 of 108 bit address register bit description 7 6 5 4 3 2 1 0 comments notes 1 contrast reduction mode enabled C fb signal interpreted as tri-level signal fb_sp_adjust 0 1 0 0 adjusts fb timing in reference to the sampling clock each lsb corresponds to 1/8 of a clock cycle fb_delay[3:0] 0 1 0 0 delay on fb signal in 28.63636 mhz clock cycles 0xf0 fb_control 4 reserved. 0 1 0 0 0 sd rgb input for fb on ain7, ain8 and ain9 rgb_ip_sel 1 sd rgb input for fb on ain4, ain5 and ain6 reserved. 0 set to zero 0 0 25% 0 1 50% 1 0 75% cntr_mode[1:0]. allows adjustment of contrast level in the contrast reduction box. 1 1 100% 0 0 cntr_enable = 0, fb threshold = 1.4 v cntr_enable C 1, fb threshold = 1.6 v 0 1 cntr_enable = 0, fb threshold = 1.6 v cntr_enable C 1, fb threshold = 1.8 v 1 0 cntr_enable = 0, fb threshold = 1.8 v cntr_enable C 1, fb threshold = 2 v fb_level[1:0]. controls reference level for fast blank comparator. 1 1 cntr_enable = 0, fb threshold = 2 v cntr_enable C 1, fb threshold = not used 0 0 0.4 v contrast reduction threshold 0 1 0.6 v contrast reduction threshold 1 0 0.8 v contrast reduction threshold cntr_enable = 1 0xf1 fb_control 5 cntr_level[1:0]. controls reference level for contrast reduction comparator. 11 not used 0 disables the internal antialiasing filter on channel 0 aa_filt_en[0] 1 enables the internal antialiasing filter on channel 0 0 disables the internal antialiasing filter on channel 1 aa_filt_en[1] 1 enables the internal antialiasing filter on channel 1 0 disables the internal antialiasing filter on channel 2 aa_filt_en[2] 1 enables the internal antialiasing filter on channel 2 0 disables the internal antialiasing filter on channel 3 aa_filt_en[3] 1 enables the internal antialiasing filter on channel 3 0 0 0 0 no connection 0 0 0 1 no connection 0 0 1 0 no connection 0 0 1 1 no connection 0100 ain4 0 1 0 1 no connection 0 1 1 0 no connection 0 1 1 1 no connection 1 0 0 0 no connection 1001 ain7 1 0 1 0 no connection 1 0 1 1 no connection 0xf3 afe_ control 1 adc3_sw[3:0] 1 1 0 0 no connection
ADV7184 rev. 0 | page 89 of 108 bit address register bit description 7 6 5 4 3 2 1 0 comments notes 1 1 0 1 no connection 1 1 1 0 no connection 1 1 1 1 no connection 0 0 reserved 0 1 medium-low drive strength (2x) 1 0 medium-high drive strength (3x) dr_str_s[1:0]. selects the drive strength for the sync output signals. 1 1 high drive strength (4x) 0 0 reserved 0 1 medium-low drive strength (2x) 1 0 medium-high drive strength (3x) dr_str_c[1:0]. selects the drive strength for the clock output signal. 1 1 high drive strength (4x) 00 reserved 0 1 medium-low drive strength (2x) 1 0 medium-high drive strength (3x) dr_str[1:0]. selects the drive strength for the data output signals. can be increased or decreased for emc or crosstalk reasons. 11 high drive strength (4x) 0xf4 drive strength reserved. x x no delay 0 0 0 bypass mode 0db 2 mhz 5 mhz 0 0 1 ?3 db +2 db 0 1 0 ?6 db +3.5 db 0 1 1 ?10 db +5 db ntsc filters 1 0 0 reserved 3 mhz 6 mhz 1 0 1 ?2 db +2 db 1 1 0 ?5 db +3 db iffiltsel[2:0] if filter selection for pal and ntsc 1 1 1 ?7 db +5 db pal filters 0xf8 if comp control reserved. 0 0 0 0 0 0 limit maximum vsync frequency to 66.25 hz (475 lines/frame) extend_vs_max_freq 1 limit maximum vsync frequency to 70.09 hz (449 lines/frame) 0 limit minimum vsync frequency to 42.75 hz (731 lines/frame) extend_vs_min_freq 1 limit minimum vsync frequency to 39.51 hz (791 lines/frame) 0 0 auto coast mode 0 1 50 hz coast mode 1 0 60 hz coast mode vs_coast_mode[1:0] 1 1 reserved this value sets up the output coast frequency. 0xf9 vs mode control reserved. 0 0 0 0 0xfb peaking control peaking_gain[7:0] 0 1 0 0 0 0 0 0 increases/decreases the gain for high frequency portions of the video signal 0xfc coring threshold 2 dnr_th2[7:0] 0 0 0 0 0 1 0 0 specifies the max. edge that is interpreted as noise and therefore blanked
ADV7184 rev. 0 | page 90 of 108 user sub map the collective name for the subaddress registers in table 103 is user sub map. to access the user sub map, sub_usr_en in register address 0x0e (user map) must be programmed to 1. table 103. user sub map register details address reset dec hex register name r w 7 6 5 4 3 2 1 0 value (hex) 64 40 interrupt configuration 0 rw intrq_dur_ sel.1 intrq_dur_ sel.0 mv_intrq_ sel.1 mv_intrq_ sel.0 mpu_stim_i ntrq intrq_op_ sel.1 intrq_op_ sel.0 0001x000 10 66 42 interrupt status 1 r mv_ps_cs_q sd_fr_ hng_q sd_unlock_q sd_lock_q --- --- 67 43 interrupt clear 1 w mv_ps_cs_clr sd_fr_ chng_clr sd_unlock_ clr sd_lock_clr x0000000 00 68 44 interrupt mask 1 rw mv_ps_cs _mskb sd_fr_ chng_mskb sd_unlock_ mskb sd_lock_ mskb x0000000 00 69 45 raw status 2 r mpu_stim_ intrq even_field ccapd --- --- 70 46 interrupt status 2 r mpu_stim_i ntrq_q sd_field_ chngd_q gemd_q ccapd_q --- --- 71 47 interrupt clear 2 w mpu_stim_ intrq_clr sd_field_ chngd_clr gemd_clr ccapd_clr 0xx00000 00 72 48 interrupt mask 2 rw mpu_stim_ intrq_mskb sd_field_ chngd_ mskb gemd_mskb ccapd_mskb 0xx00000 00 73 49 raw status 3 r scm_lock sd_h_lock sd_v_lock sd_op_50hz --- --- 74 4a interrupt status 3 r pal_sw_lk_ chng_q scm_lock_ chng_q sd_ad_chng_q sd_h_lock_ chng_q sd_v_lock_ chng_q sd_op_ chng_q --- --- 75 4b interrupt clear 3 w pal_sw_lk_ chng_clr scm_lock_ chng_clr sd_ad_chng_ clr sd_h_lock_ chng_clr sd_v_lock_ chng_clr sd_op_ chng_clr xx000000 00 76 4c interrupt mask 3 rw pal_sw_lk_ chng_mskb scm_lock_ chng_mskb sd_ad_chng_ mskb sd_h_lock_ chng_mskb sd_v_lock_ chng_mskb sd_op_ chng_mskb xx000000 00 78 4e interrupt status 4 r vdp_ vitc_q vdp_gs_ vps_pdc_ utc_chng_q vdp_ cgms_wss_ chngd_q vdp_ccapd_ q --- --- 79 4f interrupt clear 4 w vdp_ vitc_clr vdp_gs_vps_ pdc_utc_ chng_clr vdp_cgms_wss_ chngd_clr vdp_ccapd_ clr 00x0x0x0 00 80 50 interrupt mask 4 rw vdp_ vitc_mskb vdp_gs_vps_ pdc_utc_ chng_mskb vdp_cgms_wss_ chngd_mskb vdp_ccapd_ mskb 00x0x0x0 00 96 60 vdp_config_1 rw wst_pkt_ decod_disable vdp_ttxt_type_ man_enable vdp_ttxt_ type_man.1 vdp_ttxt_ type_man.0 10001000 88 97 61 vdp_config_2 rw auto_detect_ gs_type 0001xx00 10 98 62 vdp_adf_config_1 rw adf_enable adf_mode.1 adf_mode.0 adf_did.4 adf_did.3 adf_did.2 adf_did.1 adf_did.0 00010101 15 99 63 vdp_adf_config_2 rw duplicate adf adf_sdid.5 adf_ sdid.4 adf_sdid.3 adf_sdid.2 adf_sdid.1 adf_sdid.0 0x101010 2a 100 64 vdp_line_00e rw man_line_pgm vbi_data_ p318.3 vbi_data_ p318.2 vbi_data_ p318.1 vbi_data_ p318.0 0xxx0000 00 101 65 vdp_line_00f rw vbi_data_p6_ n23.3 vbi_data_ p6_n23.2 vbi_data_ p6_n23.1 vbi_data_ p6_n23.0 vbi_data_p319_ n286.3 vbi_data_p319_ n286.2 vbi_data_ p319_n286.1 vbi_data_ p319_n286.0 00000000 00 102 66 vdp_line_010 rw vbi_data_p7_ n24.3 vbi_data_ p7_n24.2 vbi_data_ p7_n24.1 vbi_data_ p7_n24.0 vbi_data_p320_ n287.3 vbi_data_p320_ n287.2 vbi_data_ p320_n287.1 vbi_data_ p320_n287.0 00000000 00 103 67 vdp_line_011 rw vbi_data_p8_ n25.3 vbi_data_ p8_n25.2 vbi_data_ p8_n25.1 vbi_data_ p8_n25.0 vbi_data_p321_ n288.3 vbi_data_p321_ n288.2 vbi_data_ p321_n288.1 vbi_data_ p321_n288.0 00000000 00 104 68 vdp_line_012 rw vbi_data_p9.3 vbi_data_ p9.2 vbi_data_ p9.1 vbi_data_ p9.0 vbi_data_ p322.3 vbi_data_p322.2 vbi_data_ p322.1 vbi_data_ p322.0 00000000 00 105 69 vdp_line_013 rw vbi_data_p10. 3 vbi_data_ p10.2 vbi_data_ p10.1 vbi_data_ p10.0 vbi_data_p323.3 vbi_data_p323.2 vbi_data_ p323.1 vbi_data_ p323.0 00000000 00 106 6a vdp_line_014 rw vbi_data_p11. 3 vbi_data_ p11.2 vbi_data_ p11.1 vbi_data_ p11.0 vbi_data_p324_ n272.3 vbi_data_p324_ n272.2 vbi_data_ p324_n272.1 vbi_data_ p324_n272.0 00000000 00 107 6b vdp_line_015 rw vbi_data_p12_ n10.3 vbi_data_ p12_n10.2 vbi_data_ p12_n10.1 vbi_data_ p12_n10.0 vbi_data_p325_ n273.3 vbi_data_p325_ n273.2 vbi_data_ p325_n273.1 vbi_data_ p325_n273.0 00000000 00 108 6c vdp_line_016 rw vbi_data_p13_ n11.3 vbi_data_ p13_n11.2 vbi_data_ p13_n11.1 vbi_data_ p13_n11.0 vbi_data_p326_ n274.3 vbi_data_p326_ n274.2 vbi_data_ p326_n274.1 vbi_data_ p326_n274.0 00000000 00 109 6d vdp_line_017 rw vbi_data_p14_ n12.3 vbi_data_ p14_n12.2 vbi_data_ p14_n12.1 vbi_data_ p14_n12.0 vbi_data_p327_ n275.3 vbi_data_p327_ n275.2 vbi_data_ p327_n275.1 vbi_data_ p327_n275.0 00000000 00 110 6e vdp_line_018 rw vbi_data_p15_ n13.3 vbi_data_p15_ n13.2 vbi_data_ p15_n13.1 vbi_data_p15_ n13.0 vbi_data_p328_ n276.3 vbi_data_p328_ n276.2 vbi_data_ p328_n276.1 vbi_data_ p328_n276.0 00000000 00 111 6f vdp_line_019 rw vbi_data_p16_ n14.3 vbi_data_p16_ n14.2 vbi_data_ p16_n14.1 vbi_data_p16_ n14.0 vbi_data_p329_ n277.3 vbi_data_p329_ n277.2 vbi_data_ p329_n277.1 vbi_data_ p329_n277.0 00000000 00 112 70 vdp_line_01a rw vbi_data_p17_ n15.3 vbi_data_p17_ n15.2 vbi_data_ p17_n15.1 vbi_data_p17_ n15.0 vbi_data_p330_ n278.3 vbi_data_p330_ n278.2 vbi_data_ p330_n278.1 vbi_data_ p330_n278.0 00000000 00
ADV7184 rev. 0 | page 91 of 108 address reset dec hex register name r w 7 6 5 4 3 2 1 0 value (hex) 113 71 vdp_line_01b rw vbi_data_p18_ n16.3 vbi_data_p18_ n16.2 vbi_data_ p18_n16.1 vbi_data_p18_ n16.0 vbi_data_p331_ n279.3 vbi_data_p331_ n279.2 vbi_data_ p331_n279.1 vbi_data_ p331_n279.0 00000000 00 114 72 vdp_line_01c rw vbi_data_p19_ n17.3 vbi_data_ p19_n17.2 vbi_data_p19_ n17.1 vbi_data_p19_ n17.0 vbi_data_p332_ n280.3 vbi_data_p332_ n280.2 vbi_data_ p332_n280.1 vbi_data_ p332_n280.0 00000000 00 115 73 vdp_line_01d rw vbi_data_p20_ n18.3 vbi_data_ p20_n18.2 vbi_data_p20_ n18.1 vbi_data_p20_ n18.0 vbi_data_p333_ n281.3 vbi_data_p333_ n281.2 vbi_data_ p333_n281.1 vbi_data_ p333_n281.0 00000000 00 116 74 vdp_line_01e rw vbi_data_p21_ n19.3 vbi_data_ p21_n19.2 vbi_data_p21_ n19.1 vbi_data_p21_ n19.0 vbi_data_p334_ n282.3 vbi_data_p334_ n282.2 vbi_data_ p334_n282.1 vbi_data_ p334_n282.0 00000000 00 117 75 vdp_line_01f rw vbi_data_p22_ n20.3 vbi_data_ p22_n20.2 vbi_data_p22_ n20.1 vbi_data_p22_ n20.0 vbi_data_p335_ n283.3 vbi_data_p335_ n283.2 vbi_data_ p335_n283.1 vbi_data_ p335_n283.0 00000000 00 118 76 vdp_line_020 rw vbi_data_p23_ n21.3 vbi_data_ p23_n21.2 vbi_data_p23_ n21.1 vbi_data_p23_ n21.0 vbi_data_p336_ n284.3 vbi_data_p336_ n284.2 vbi_data_ p336_n284.1 vbi_data_ p336_n284.0 00000000 00 119 77 vdp_line_021 rw vbi_data_p24_ n22.3 vbi_data_ p24_n22.2 vbi_data_p24_ n22.1 vbi_data_p24_ n22.0 vbi_data_p337_ n285.3 vbi_data_p337_ n285.2 vbi_data_ p337_n285.1 vbi_data_ p337_n285.0 00000000 00 120 78 vdp_status_clear w vitc_clear gs_pdc_vps_ utc_clear cgms_wss_ clear cc_clear 00000000 00 120 78 vdp_status r ttxt_avl vitc_avl gs_data_type gs_pdc_vps_ utc_avl cgms_wss_avl cc_ even_field cc_avl --- --- 121 79 vdp_ccap_data_0 r ccap_byte_1.7 ccap_ byte_1.6 ccap_byte_1.5 ccap_byte_1.4 ccap_byte_1 .3 ccap_byte_1.2 ccap_byte_1.1 ccap_ byte_1.0 --- --- 122 7a vdp_ccap_data_1 r ccap_byte_2.7 ccap_ byte_2.6 ccap_byte_2.5 ccap_byte_2.4 ccap_ byte_2.3 ccap_byte_2.2 ccap_byte_2.1 ccap_ byte_2.0 --- --- 125 7d cgms_wss_data_0 r zero zero zero zero cgms_crc.5 cgms_crc.4 cgms_crc.3 cgms_crc.2 --- --- 126 7e cgms_wss_data_1 r cgms_crc.1 cgms_crc.0 cgms_wss.13 cgms_wss.12 cgms_wss.11 cgms_wss.10 cgms_wss.9 cgms_wss.8 --- --- 127 7f cgms_wss_data_2 r cgms_wss.7 cgms_wss.6 cgms_wss.5 cgms_wss.4 cgms_wss.3 cgms_wss.2 cgms_wss.1 cgms_wss.0 --- --- 132 84 vdp_gs_vps_ pdc_utc_0 r gs_vps_pdc_ utc_byte_0.7 gs_vps_pdc_ utc_byte_0.6 gs_vps_pdc_ utc_byte_0.5 gs_vps_pdc_ utc_byte_0.4 gs_vps_pdc_ utc_byte_0.3 gs_vps_pdc_ utc_byte_0.2 gs_vps_pdc_ utc_byte_0.1 gs_vps_pdc_ utc_byte_0.0 --- --- 133 85 vdp_gs_vps_ pdc_utc_1 r gs_vps_pdc_ utc_byte_1.7 gs_vps_pdc_ utc_byte_1.6 gs_vps_pdc_ utc_byte_1.5 gs_vps_pdc_ utc_byte_1.4 gs_vps_pdc_ utc_byte_1.3 gs_vps_pdc_ utc_byte_1.2 gs_vps_pdc_ utc_byte_1.1 gs_vps_pdc_ utc_byte_1.0 --- --- 134 86 vdp_gs_vps_ pdc_utc_2 r gs_vps_pdc_ utc_byte_2.7 gs_vps_pdc_ utc_byte_2.6 gs_vps_pdc_ utc_byte_2.5 gs_vps_pdc_ utc_byte_2.4 gs_vps_pdc_ utc_byte_2.3 gs_vps_pdc_ utc_byte_2.2 gs_vps_pdc_ utc_byte_2.1 gs_vps_pdc_ utc_byte_2.0 --- --- 135 87 vdp_gs_vps_ pdc_utc_3 r gs_vps_pdc_ utc_byte_3.7 gs_vps_pdc_ utc_byte_3.6 gs_vps_pdc_ utc_byte_3.5 gs_vps_pdc_ utc_byte_3.4 gs_vps_pdc_ utc_byte_3.3 gs_vps_pdc_ utc_byte_3.2 gs_vps_pdc_ utc_byte_3.1 gs_vps_pdc_ utc_byte_3.0 --- --- 136 88 vdp_vps_pdc_ utc_4 r vps_pdc_utc_ byte_4.7 vps_pdc_utc_ byte_4.6 vps_pdc_utc_ byte_4.5 vps_pdc_utc_ byte_4.4 vps_pdc_utc_ byte_4.3 vps_pdc_utc_ byte_4.2 vps_pdc_utc_ byte_4.1 vps_pdc_ utc_byte_4.0 --- --- 137 89 vdp_vps_pdc_ utc_5 r vps_pdc_utc_ byte_5.7 vps_pdc_utc_ byte_5.6 vps_pdc_utc_ byte_5.5 vps_pdc_utc_ byte_5.4 vps_pdc_utc_ byte_5.3 vps_pdc_utc_ byte_5.2 vps_pdc_utc_ byte_5.1 vps_pdc_ utc_byte_5.0 --- --- 138 8a vdp_vps_pdc_ utc_6 r vps_pdc_utc_ byte_6.7 vps_pdc_utc_ byte_6.6 vps_pdc_utc_ byte_6.5 vps_pdc_utc_ byte_6.4 vps_pdc_utc_ byte_6.3 vps_pdc_utc_ byte_6.2 vps_pdc_utc_ byte_6.1 vps_pdc_ utc_byte_6.0 --- --- 139 8b vdp_vps_pdc_ utc_7 r vps_pdc_utc_ byte_7.7 vps_pdc_utc_ byte_7.6 vps_pdc_utc_ byte_7.5 vps_pdc_utc_ byte_7.4 vps_pdc_utc_ byte_7.3 vps_pdc_utc_ byte_7.2 vps_pdc_utc_ byte_7.1 vps_pdc_ utc_byte_7.0 --- --- 140 8c vdp_vps_pdc_ utc_8 r vps_pdc_utc_ byte_8.7 vps_pdc_utc_ byte_8.6 vps_pdc_utc_ byte_8.5 vps_pdc_utc_ byte_8.4 vps_pdc_utc_ byte_8.3 vps_pdc_utc_ byte_8.2 vps_pdc_utc_ byte_8.1 vps_pdc_ utc_byte_8.0 --- --- 141 8d vdp_vps_pdc_ utc_9 r vps_pdc_utc_ byte_9.7 vps_pdc_utc_ byte_9.6 vps_pdc_utc_ byte_9.5 vps_pdc_utc_ byte_9.4 vps_pdc_utc_ byte_9.3 vps_pdc_utc_ byte_9.2 vps_pdc_utc_ byte_9.1 vps_pdc_ utc_byte_9.0 --- --- 142 8e vdp_vps_pdc_ utc_10 r vps_pdc_utc_ byte_10.7 vps_pdc_utc_ byte_10.6 vps_pdc_utc_ byte_10.5 vps_pdc_utc_ byte_10.4 vps_pdc_utc_ byte_10.3 vps_pdc_utc_ byte_10.2 vps_pdc_utc_ byte_10.1 vps_pdc_ utc_byte_10.0 --- --- 143 8f vdp_vps_pdc_ utc_11 r vps_pdc_utc_ byte_11.7 vps_pdc_utc_ byte_11.6 vps_pdc_utc_ byte_11.5 vps_pdc_utc_ byte_11.4 vps_pdc_utc_ byte_11.3 vps_pdc_utc_ byte_11.2 vps_pdc_utc_ byte_11.1 vps_pdc_ utc_byte_11.0 --- --- 144 90 vdp_vps_pdc_ utc_12 r vps_pdc_utc_ byte_12.7 vps_pdc_utc_ byte_12.6 vps_pdc_utc_ byte_12.5 vps_pdc_utc_ byte_12.4 vps_pdc_utc_ byte_12.3 vps_pdc_utc_ byte_12.2 vps_pdc_utc_ byte_12.1 vps_pdc_ utc_byte_12.0 --- --- 146 92 vdp_vitc_data_0 r vitc_data_1.7 vitc_data_1.6 vitc_data_1.5 vitc_data_1.4 vitc_data_1.3 vitc_data_1.2 vitc_data_1.1 vitc_data_1.0 --- --- 147 93 vdp_vitc_data_1 r vitc_data_2.7 vitc_data_2.6 vitc_data_2.5 vitc_data_2.4 vitc_data_2.3 vitc_data_2.2 vitc_data_2.1 vitc_data_2.0 --- --- 148 94 vdp_vitc_data_2 r vitc_data_3.7 vitc_data_3.6 vitc_data_3.5 vitc_data_3.4 vitc_data_3.3 vitc_data_3.2 vitc_data_3.1 vitc_data_3.0 --- --- 149 95 vdp_vitc_data_3 r vitc_data_4.7 vitc_data_4.6 vitc_data_4.5 vitc_data_4.4 vitc_data_4.3 vitc_data_4.2 vitc_data_4.1 vitc_data_4.0 --- --- 150 96 vdp_vitc_data_4 r vitc_data_5.7 vitc_data_5.6 vitc_data_5.5 vitc_data_5.4 vitc_data_5.3 vitc_data_5.2 vitc_data_5.1 vitc_data_5.0 --- --- 151 97 vdp_vitc_data_5 r vitc_data_6.7 vitc_data_6.6 vitc_data_6.5 vitc_data_6.4 vitc_data_6.3 vitc_data_6.2 vitc_data_6.1 vitc_data_6.0 --- --- 152 98 vdp_vitc_data_6 r vitc_data_7.7 vitc_data_7.6 vitc_data_7.5 vitc_data_7.4 vitc_data_7.3 vitc_data_7.2 vitc_data_7.1 vitc_data_7.0 --- --- 153 99 vdp_vitc_data_7 r vitc_data_8.7 vitc_data_8.6 vitc_data_8.5 vitc_data_8.4 vitc_data_8.3 vitc_data_8.2 vitc_data_8.1 vitc_data_8.0 --- --- 154 9a vdp_vitc_data_8 r vitc_data_9.7 vitc_data_9.6 vitc_data_9.5 vitc_data_9.4 vitc_data_9.3 vitc_data_9.2 vitc_data_9.1 vitc_data_9.0 --- --- 155 9b vdp_vitc_calc_crc r vitc_crc.7 vitc_crc.6 vitc _crc.5 vitc_crc.4 vitc_crc.3 vitc_crc.2 vitc_crc.1 vitc_crc.0 --- --- 156 9c vdp_output_sel rw i2c_gs_vps_ pdc_utc.1 i2c_gs_vps_ pdc_utc.0 gs_vps_pdc_ utc_cb_change wss_cgms_ cb_change 00110000 30
ADV7184 rev. 0 | page 92 of 108 table 104 provides a detailed description of the registers located in the user sub map. table 104. user sub map detailed description user sub map bit address register bit description 7 6 5 4 3 2 1 0 comments notes 0 0 open drain 01drive low when active 10drive high when active intrq_op_sel[1:0]. interrupt drive level select 11reserved 0 manual interru pt mode disabled mpu_stim_intrq[1:0]. manual interrupt set mode 1 manual interrupt mode enabled reserved x not used 00 reserved 0 1 pseudo sync only 1 0 color stripe only mv_intrq_sel[1:0]. macrovision interrupt select 1 1 pseudo sync or color stripe 0 0 3 xtal periods 01 15 xtal periods 10 63 xtal periods 0x40 interrupt configuration 1 intrq_dur_sel[1:0]. interrupt duration select 1 1 active until cleared 0no change sd_lock_q 1 sd input has caused the decoder to go from an unlocked state to a locked state 0 no change sd_unlock_q 1 sd input has caused the decoder to go from a locked state to an unlocked state reserved x reserved x reserved x 0 no change sd_fr_chng_q 1 denotes a change in the free-run status 0 no change mv_ps_cs_q 1 pseudo sync/color striping detected. see reg 0x40 mv_intrq_sel[1:0] for selection 0x42 interrupt status 1 (read only) reserved x these bits can be cleared or masked in registers 0x43 and 0x44, respectively. 0 do not clear sd_lock_clr 1 clears sd_lock_q bit 0 do not clear sd_unlock_clr 1 clears sd_unlock_q bit reserved 0 not used reserved 0 not used reserved 0 not used 0 do not clear sd_fr_chng_clr 1 clears sd_fr_chng_q bit 0 do not clear mv_ps_cs_clr 1 clears mv_ps_cs_q bit 0x43 interrupt clear 1 (write only) reserved x not used 0 masks sd_lock_q bit sd_lock_mskb 1unmasks sd_lock_q bit 0 masks sd_unlock_q bit sd_unlock_mskb 1 unmasks sd_unlock_q bit reserved 0 not used reserved 0 not used reserved 0 not used 0 masks sd_fr_chng_q bit sd_fr_chng_mskb 1 unmasks sd_fr_chng_q bit 0 masks mv_ps_cs_q bit mv_ps_cs_mskb 1 unmasks mv_ps_cs_q bit 0x44 interrupt mask 1 (read/write) reserved x not used
ADV7184 rev. 0 | page 93 of 108 user sub map bit address register bit description 7 6 5 4 3 2 1 0 comments notes 0no ccapd data detected C vbi system 2 ccapd 1ccapd data detected C vbi system 2 reserved xxx 0 current sd field is odd numbered even_field 1 current sd field is even numbered reserved xx 0 mpu_stim_int = 0 0x45 raw status 2 (read only) mpu_stim_intrq 1 mpu_stim_int = 1 these bits are status bits only. they cannot be cleared or masked. register 0x46 is used for this purpose. 0closed captioning not detected in the input video signal C vbi system 2 ccapd_q 1closed captioning data detected in the video input signal C vbi system 2 0 gemstar data not detected in the input video signalC vbi system 2 gemd_q 1 gemstar data detected in the input video signalC vbi system 2 reserved xx 0 sd signal has not changed field from odd to even or vice versa sd_field_chngd_q 1 sd signal has changed field from odd to even or vice versa reserved x not used reserved x not used 0 manual interrupt not set 0x46 interrupt status 2 (read only) mpu_stim_intrq_q 1 manual interrupt set these bits can be cleared or masked by registers 0x47 and 0x48, respectively. note that interrupt in register 0x46 for the ccap, gemstar, cgms and wss data is using the mode 1 data slicer. 0 do not clear C vbi system 2 ccapd_clr 1 clears ccapd_q bit C vbi system 2 0 do not clear gemd_clr 1 clears gemd_q bit reserved x x 0 do not clear sd_field_chngd_clr 1 clears sd_field_chngd_q bit reserved x not used reserved x not used 0 do not clear 0x47 interrupt clear 2 (write only) mpu_stim_intrq_clr 1 clears mpu_stim_intrq_q bit note that interrupt in register 0x46 for the ccap, gemstar, cgms and wss data is using the mode 1 data slicer. 0 masks ccapd_q bit C vbi system 2 ccapd_mskb 1unmasks ccapd_q bit C vbi system 2 0 masks gemd_q bit C vbi system 2 gemd_mskb 1 unmasks gemd_q bit C vbi system 2 reserved 0 0 not used 0 masks sd_field_chngd_q bit sd_field_chngd_mskb 1 unmasks sd_field_chngd_q bit reserved 0 0 not used 0 masks mpu_stim_intrq_q bit 0x48 interrupt mask 2 (read/write) mpu_stim_intrq_mskb 1 unmasks mpu_stim_intrq_q bit note that interrupt in register 0x46 for the ccap, gemstar, cgms and wss data is using the mode 1 data slicer. 0sd 60 hz signal output sd_op_50hz. sd 60/50hz frame rate at output 1sd 50 hz signal output 0 sd vertical sync lock not established sd_v_lock 1 sd vertical sync lock established 0 sd horizontal sync lock not established sd_h_lock 1 sd horizontal sync lock established reserved x not used 0 secam lock not established scm_lock 1 secam lock established reserved x not used reserved x not used 0x49 raw status 3 (read only) reserved x not used these bits are status bits only. they cannot be cleared or masked. register 0x4a is used for this purpose.
ADV7184 rev. 0 | page 94 of 108 user sub map bit address register bit description 7 6 5 4 3 2 1 0 comments notes 0 no change in sd signal standard detected at the output sd_op_chng_q. sd 60/50 hz frame rate at output 1 a change in sd signal standard is detected at the output 0 no change in sd vertical sync lock status sd_v_lock_chng_q 1 sd vertical sync lock status has changed 0 no change in sd horizontal sync lock status sd_h_lock_chng_q 1 sd horizontal sync lock status has changed x no change in ad_result[2:0] bits in status register 1 sd_ad_chng_q. sd autodetect changed ad_result[2:0] bits in status register 1 have changed 0 no change in secam lock status scm_lock_chng_q. secam lock 1 secam lock status has changed x no change in pal swinging burst lock status pal_sw_lk_chng_q pal swinging burst lock status has changed reserved x not used 0x4a interrupt status 3 (read only) reserved x not used these bits can be cleared and masked by registers 0x4b and 0x4c, respectively. 0 do not clear sd_op_chng_clr 1clears sd_op_chng_q bit 0 do not clear sd_v_lock_chng_clr 1 clears sd_v_lock_chng_q bit 0 do not clear sd_h_lock_chng_clr 1 clears sd_h_lock_chng_q bit 0 do not clear sd_ad_chng_clr 1 clears sd_ad_chng_q bit 0 do not clear scm_lock_chng_clr 1 clears scm_lock_chng_q bit 0 do not clear pal_sw_lk_chng_clr 1 clears pal_sw_lk_chng_q bit reserved x not used 0x4b interrupt clear 3 (write only) reserved x not used 0 masks sd_op_chng_q bit sd_op_chng_mskb 1unmasks sd_op_chng_q bit 0 masks sd_v_lock_chng_q bit sd_v_lock_chng_ mskb 1 unmasks sd_v_lock_chng_q bit 0 masks sd_h_lock_chng_q bit sd_h_lock_chng_ mskb 1 unmasks sd_h_lock_chng_q bit 0 masks sd_ad_chng_q bit sd_ad_chng_ mskb 1 unmasks sd_ad_chng_q bit 0 masks scm_lock_chng_q bit scm_lock_chng_ mskb 1 unmasks scm_lock_chng_q bit 0 masks pal_sw_lk_chng_q bit pal_sw_lk_chng_ mskb 1 unmasks pal_sw_lk_chng_q bit reserved x not used 0x4c interrupt mask 2 (read/write) reserved x not used 0closed captioning not detected vdp_ccapd_q 1closed captioning detected reserved x 0 cgms/wss data is not changed/not available vdp_cgms_wss_chngd_q. see 0x9c bit 4of user sub map to determine whether interrupt is issued for a change in detected data or for when data is detected regardless of content 1 cgms/wss data is changed/available reserved x 0x4e interrupt status 4 (read only) vdp_gs_vps_pdc_utc_chng_q. see 0x9c bit 5of user sub map to determine 0 gemstar/pdc/vps/utc data is not changed/available these bits can be cleared and masked by registers 0x4f and 0x50, respectively. note that interrupt in register 0x4e for the ccap, gemstar, cgms, wss,vps,pdc, utc and vitc data is using the vdp data slicer.
ADV7184 rev. 0 | page 95 of 108 user sub map bit address register bit description 7 6 5 4 3 2 1 0 comments notes whether interrupt is issued for a change in detected data or for when data is detected regardless of content 1 gemstar/pdc/vps/utc data is changed/available reserved x 0 vitc data is not available in the vdp vdp_vitc_q 1 vitc data is available in the vdp reserved x 0do not clear vdp_ccapd_clr 1 clears vdp_ccapd_q reserved x 0 do not clear vdp_cgms_wss_chngd_clr 1 clears vdp_cgms_wss_chngd_q reserved x 0 do not clear vdp_gs_vps_pdc_utc_ chng_clr 1 clears vdp_gs_vps_pdc_utc_chng_q reserved x 0 do not clear vdp_vitc_clr 1 clears vdp_vitc_q 0x4f interrupt clear 4 (write only) reserved x note that interrupt in register 0x4e for the ccap, gemstar, cgms, wss,vps,pdc, utc and vitc data is using the vdp data slicer. 0masks vdp_ccapd_q vdp_ccapd_mskb 1unmasks vdp_ccap_d_q reserved x 0 masks vdp_cgms_wss_chngd_q vdp_cgms_wss_chngd_mskb 1 unmasks vdp_cgms_wss_chngd_q reserved x 0 masks vdp_gs_vps_pdc_utc_chng_q vdp_gs_vps_pdc_utc_ chng_mskb 1 unmasks vdp_gs_vps_pdc_utc_chng_q reserved x 0 masks vdp_vitc_q vdp_vitc_mskb 1 unmasks vdp_vitc_q 0x50 interrupt mask 4 reserved x note that interrupt in register 0x4e for the ccap, gemstar, cgms, wss,vps,pdc, utc and vitc data is using the vdp data slicer. 0 0 pal: teletext-itu-bt.653-625/50-a ntsc: reserved 0 1 pal: teletext-itu-bt.653-625/50-b (wst) ntsc: teletext-itu-bt.653-525/60-b 1 0 pal: teletext-itu-bt.653-625/50-c ntsc: teletext-itu-bt.653-525/60-c or eia516 (nabts) vdp_ttxt_type_man[1:0] 1 1 pal: teletext-itu-bt.653-625/50-d ntsc: teletext-itu-bt.653-525/60-d 0 user programming of teletext type disabled vdp_ttxt_type_man_enable 1 user programming of teletext type enabled 0 enable hamming decoding of wst packets wst_pkt_decod_disable 1 disable hamming decoding of wst packets 0x60 vdp_config_1 reserved 1 0 0 0 reserved x x 0 0 0 disable autodetection of gemstar type auto_detect_gs_type 1 enable autodetection of gemstar type 0x61 vdp_config_2 reserved 0 0 0 adf_did[4:0] 1 0 1 0 1 user specified did sent in the ancillary data stream with vdp decoded data 0 0 nibble mode 0x62 vdp_adf_config_1 adf_mode[1:0] 0 1 byte mode, no code restrictions
ADV7184 rev. 0 | page 96 of 108 user sub map bit address register bit description 7 6 5 4 3 2 1 0 comments notes 1 0 byte mode with 0x00 and 0xff prevented 11 reserved 0 disable insertion of vbi decoded data into ancillary 656 stream adf_enable 1 enable insertion of vbi decoded data into ancillary 656 stream adf_sdid[5:0] 1 0 1 0 1 0 user-specified sdid sent in the ancillary data stream with vdp decoded data reserved x 0 ancillary data packet is spread across the y and c data streams 0x63 vdp_adf_config_2 duplicate_adf 1 ancillary data packet is duplicated on the y and c data streams vbi_data_p318[3:0] 0 0 0 0 sets vbi standard to be decoded from line 318 (pal). ntsc C n/a reserved 0 0 0 man_line_pgm 0 decode default standards on the lines indicated in table 64. 0x64 vdp_line_00e 1 manually program the vbi standard to be decoded on each line. see table 65 if set to 1, all vbi_data_px_ny bits must set as desired. vbi_data_p319_n286[3:0] 0 0 0 0 sets vbi standard to be decoded from line 319 (pal), 286 (ntsc) 0x65 vdp_line_00f vbi_data_p6_n23[3:0] 0 0 0 0 sets vbi standard to be decoded from line 6 (pal), 23 (ntsc) man_line_pgm must be set to 1 for these bits to be effective vbi_data_p320_n287[3:0] 0 0 0 0 sets vbi standard to be decoded from line 320 (pal), 287 (ntsc) 0x66 vdp_line_010 vbi_data_p7_n24[3:0] 0 0 0 0 sets vbi standard to be decoded from line 7 (pal), 24 (ntsc) man_line_pgm must be set to 1 for these bits to be effective vbi_data_p321_n288[3:0] 0 0 0 0 sets vbi standard to be decoded from line 321 (pal), 288 (ntsc) 0x67 vdp_line_011 vbi_data_p8_n25[3:0] 0 0 0 0 sets vbi standard to be decoded from line 8 (pal), 25 (ntsc) man_line_pgm must be set to 1 for these bits to be effective vbi_data_p322[3:0] 0 0 0 0 sets vbi standard to be decoded from line 322 (pal), ntsc C n/a 0x68 vdp_line_012 vbi_data_p9[3:0] 0 0 0 0 sets vbi standard to be decoded from line 9 (pal), ntsc C n/a man_line_pgm must be set to 1 for these bits to be effective vbi_data_p323[3:0] 0 0 0 0 sets vbi standard to be decoded from line 323 (pal), ntsc Cn/a 0x69 vdp_line_013 vbi_data_p10[3:0] 0 0 0 0 sets vbi standard to be decoded from line 10 (pal), ntsc C n/a man_line_pgm must be set to 1 for these bits to be effective vbi_data_p324_n272[3:0] 0 0 0 0 sets vbi standard to be decoded from line 324 (pal), 272 (ntsc) 0x6a vdp_line_014 vbi_data_p11[3:0] 0 0 0 0 sets vbi standard to be decoded from line 11 (pal), ntsc C n/a man_line_pgm must be set to 1 for these bits to be effective vbi_data_p325_n273[3:0] 0 0 0 0 sets vbi standard to be decoded from line 325 (pal), 273(ntsc) 0x6b vdp_line_015 vbi_data_p12_n10[3:0] 0 0 0 0 sets vbi standard to be decoded from line 12 (pal), 10 (ntsc) man_line_pgm must be set to 1 for these bits to be effective vbi_data_p326_n274[3:0] 0 0 0 0 sets vbi standard to be decoded from line 326 (pal), 274 (ntsc) 0x6c vdp_line_016 vbi_data_p13_n11[3:0] 0 0 0 0 sets vbi standard to be decoded from line 13 (pal), 11 (ntsc) man_line_pgm must be set to 1 for these bits to be effective vbi_data_p327_n275[3:0] 0 0 0 0 sets vbi standard to be decoded from line 327 (pal), 275 (ntsc) 0x6d vdp_line_017 vbi_data_p14_n12[3:0] 0 0 0 0 sets vbi standard to be decoded from line 14 (pal), 12 (ntsc) man_line_pgm must be set to 1 for these bits to be effective vbi_data_p328_n276[3:0] 0 0 0 0 sets vbi standard to be decoded from line 328 (pal), 276 (ntsc) 0x6e vdp_line_018 vbi_data_p15_n13[3:0] 0 0 0 0 sets vbi standard to be decoded from line 15 (pal), 13 (ntsc) man_line_pgm must be set to 1 for these bits to be effective vbi_data_p329_n277[3:0] 0 0 0 0 sets vbi standard to be decoded from line 329 (pal), 277 (ntsc) 0x6f vdp_line_019 vbi_data_p16_n14[3:0] 0 0 0 0 sets vbi standard to be decoded from line 16 (pal), 14 (ntsc) man_line_pgm must be set to 1 for these bits to be effective 0x70 vdp_line_01a vbi_da ta_p330_n278[3:0] 0 0 0 0 sets vbi standard to be decoded from line 330 (pal), 278 (ntsc) man_line_pgm must be set to 1 for these bits to be
ADV7184 rev. 0 | page 97 of 108 user sub map bit address register bit description 7 6 5 4 3 2 1 0 comments notes vbi_data_p17_n15[3:0] 0 0 0 0 sets vbi standard to be decoded from line 17 (pal), 15 (ntsc) effective vbi_data_p331_n279[3:0] 0 0 0 0 sets vbi standard to be decoded from line 331 (pal), 279 (ntsc) 0x71 vdp_line_01b vbi_data_p18_n16[3:0] 0 0 0 0 sets vbi standard to be decoded from line 18 (pal), 16 (ntsc) man_line_pgm must be set to 1 for these bits to be effective vbi_data_p332_n280[3:0] 0 0 0 0 sets vbi standard to be decoded from line 332 (pal), 280 (ntsc) 0x72 vdp_line_01c vbi_data_p19_n17[3:0] 0 0 0 0 sets vbi standard to be decoded from line 19 (pal), 17 (ntsc) man_line_pgm must be set to 1 for these bits to be effective vbi_data_p333_n281[3:0] 0 0 0 0 sets vbi standard to be decoded from line 333 (pal), 281 (ntsc) 0x73 vdp_line_01d vbi_data_p20_n18[3:0] 0 0 0 0 sets vbi standard to be decoded from line 20 (pal), 18 (ntsc) man_line_pgm must be set to 1 for these bits to be effective vbi_data_p334_n282[3:0] 0 0 0 0 sets vbi standard to be decoded from line 334 (pal), 282 (ntsc) 0x74 vdp_line_01e vbi_data_p21_n19[3:0] 0 0 0 0 sets vbi standard to be decoded from line 21 (pal), 19 (ntsc) man_line_pgm must be set to 1 for these bits to be effective vbi_data_p335_n283[3:0] 0 0 0 0 sets vbi standard to be decoded from line 335 (pal), 283 (ntsc) 0x75 vdp_line_01f vbi_data_p22_n20[3:0] 0 0 0 0 sets vbi standard to be decoded from line 22 (pal), 20 (ntsc) man_line_pgm must be set to 1 for these bits to be effective vbi_data_p336_n284[3:0] 0 0 0 0 sets vbi standard to be decoded from line 336 (pal), 284 (ntsc) 0x76 vdp_line_020 vbi_data_p23_n21[3:0] 0 0 0 0 sets vbi standard to be decoded from line 23 (pal), 21 (ntsc) man_line_pgm must be set to 1 for these bits to be effective vbi_data_p337_n285[3:0] 0 0 0 0 sets vbi standard to be decoded from line 337 (pal), 285 (ntsc) 0x77 vdp_line_021 vbi_data_p24_n22[3:0] 0 0 0 0 sets vbi standard to be decoded from line 24 (pal), 22 (ntsc) man_line_pgm must be set to 1 for these bits to be effective 0closed captioning not detected cc_avl 1closed captioning detected cc_clear resets the cc_avl bit 0 closed captioning decoded from odd field cc_even_field 1 closed captioning decoded from even field 0 cgms/wss not detected cgms_wss_avl 1 cgms/wss detected cgms_wss_clear resets the cgms_wss_avl bit reserved 0 0 vps not detected gs_pdc_vps_utc_avl 1 vps detected gs_pdc_vps_utc_clear resets the gs_pdc_vps_utc_avl bit 0 gemstar 1x detected gs_data_type 1 gemstar 2x detected 0 vitc not detected vitc_avl 1 vitc detected vitc_clear resets the vitc_avl bit 0 teletext not detected 0x78 vdp_status (read only) ttxt_avl 1 teletext detected 0 do not re-initialize the ccap registers cc_clear 1 re-initializes the ccap readback registers this is a self-clearing bit reserved 0 0 do not re-initialize the cgms/wss registers cgms_wss_clear 1 re-initializes the cgms/wss readback registers this is a self-clearing bit reserved 0 0 do not re-initialize the gs/pdc/vps/ utc registers gs_pdc_vps_utc_clear 1 refreshes the gs/pdc/vps/utc readback registers this is a self-clearing bit reserved 0 0 do not re-initialize the vitc registers vitc_clear 1 re-initializes the vitc readback registers this is a self-clearing bit 0x78 vdp_status_clear (write only) reserved 0
ADV7184 rev. 0 | page 98 of 108 user sub map bit address register bit description 7 6 5 4 3 2 1 0 comments notes 0x79 vdp_ccap_data_0 (read only) ccap_byte_1[7:0] xxxxxxxx decoded byte 1 of ccap 0x7a vdp_ccap_data_1 (read only) ccap_byte_2[7:0] xxxxxxxx decoded byte 2 of ccap cgms_crc[5:2] x x x x decoded crc sequence for cgms 0x7d vdp_cgms_wss_data_0 (read only) reserved 0000 cgms_wss[13:8] x x x x x x decoded cgms/wss data 0x7e vdp_cgms_wss_data_1 (read only) cgms_crc[1:0] x x decoded crc sequence for cgms 0x7f vdp_cgms_wss_data_2 (read only) cgms_wss[7:0] x x x x x x x x decoded cgms/wss data 0x84 vdp_gs_vps_pdc_utc_0 (read only) gs_vps_pdc_utc_byte_0[7:0] x x x x x x x x decoded gemstar/vps/pdc/utc data 0x85 vdp_gs_vps_pdc_utc_1 (read only) gs_vps_pdc_utc_byte_1[7:0] x x x x x x x x decoded gemstar/vps/pdc/utc data 0x86 vdp_gs_vps_pdc_utc_2 (read only) gs_vps_pdc_utc_byte_2[7:0] x x x x x x x x decoded gemstar/vps/pdc/utc data 0x87 vdp_gs_vps_pdc_utc_3 (read only) gs_vps_pdc_utc_byte_3[7:0] x x x x x x x x decoded gemstar/vps/pdc/utc data 0x88 vdp_vps_pdc_utc_4 (read only) vps_pdc_utc_byte_4[7:0] x x x x x x x x decoded vps/pdc/utc data 0x89 vdp_vps_pdc_utc_5 (read only) vps_pdc_utc_byte_5[7:0] x x x x x x x x decoded vps/pdc/utc data 0x8a vdp_vps_pdc_utc_6 (read only) vps_pdc_utc_byte_6[7:0] x x x x x x x x decoded vps/pdc/utc data 0x8b vdp_vps_pdc_utc_7 (read only) vps_pdc_utc_byte_7[7:0] x x x x x x x x decoded vps/pdc/utc data 0x8c vdp_vps_pdc_utc_8 (read only) vps_pdc_utc_byte_8[7:0] x x x x x x x x decoded vps/pdc/utc data 0x8d vdp_vps_pdc_utc_9 (read only) vps_pdc_utc_byte_9[7:0] x x x x x x x x decoded vps/pdc/utc data 0x8e vdp_vps_pdc_utc_10 (read only) vps_pdc_utc_byte_10[7:0] x x x x x x x x decoded vps/pdc/utc data 0x8f vdp_vps_pdc_utc_11 (read only) vps_pdc_utc_byte_11[7:0] x x x x x x x x decoded vps/pdc/utc data 0x90 vdp_vps_pdc_utc_12 (read only) vps_pdc_utc_byte_12[7:0] x x x x x x x x decoded vps/pdc/utc data 0x92 vdp_vitc_data_0 (read only) vitc_data_0[7:0] x x x x x x x x decoded vitc data 0x93 vdp_vitc_data_1 (read only) vitc_data_1[7:0] x x x x x x x x decoded vitc data 0x94 vdp_vitc_data_2 (read only) vitc_data_2[7:0] x x x x x x x x decoded vitc data 0x95 vdp_vitc_data_3 (read only) vitc_data_3[7:0] x x x x x x x x decoded vitc data 0x96 vdp_vitc_data_4 (read only) vitc_data_4[7:0] x x x x x x x x decoded vitc data 0x97 vdp_vitc_data_5 (read only) vitc_data_5[7:0] x x x x x x x x decoded vitc data 0x98 vdp_vitc_data_6 (read only) vitc_data_6[7:0] x x x x x x x x decoded vitc data 0x99 vdp_vitc_data_7 (read only) vitc_data_7[7:0] x x x x x x x x decoded vitc data 0x9a vdp_vitc_data_8 (read only) vitc_data_8[7:0] x x x x x x x x decoded vitc data 0x9b vdp_vitc_calc_crc (read only) vitc_crc[7:0] xxxxxxxx decoded vitc crc data reserved 0 0 0 0 0 disable content-based updating of cgms and wss data wss_cgms_cb_change 1 enable content-based updating of cgms and wss data 0 disable content-based updating of gemstar, vps, pdc and utc data gs_vps_pdc_utc_cb_change 1 enable content-based updating of gemstar, vps, pdc and utc data the available bit shows the availability of data only when its content has changed. 0 0 gemstar 1x/2x 01 vps 10 pdc 0x9c vdp_output_sel i2c_gs_vps_pdc_utc[1:0] 11 utc standard expected to be decoded
ADV7184 rev. 0 | page 99 of 108 i 2 c programming examples note: these scripts are applicable to a system with the analog inputs arranged as shown in figure 50. the input selection registers change in accordance with how the pcb is laid out. mode 1 cvbs input composite video on ain10. all standards are supported through autodetect, 8-bit, 4:2:2, itu-r bt.656 output on p15 to p8. table 105. mode 1 cvbs input register address register value notes 0x00 0x0e cvbs on ain 10. 0x17 0x41 set csfm to sh1. 0x19 0xfa split filter control. 0x1d 0x47 enable 28.63636 mhz crystal mode. 0x3a 0x17 power down adc1, adc2 and adc3. 0x3b 0x71 recommended setting. 0x3d 0xa2 mwe enable manual window, color kill threshold to 2. 0x3e 0x6a blm optimization. 0x3f 0xa0 bgb optimization 0xf3 0x01 enable antialias filter on adc0. 0xf9 0x03 set maximum v lock range. 0x0e 0x80 recommended setting. 0x52 0x46 recommended setting. 0x54 0x00 recommended setting. 0x7f 0xff recommended setting. 0x81 0x30 recommended setting. 0x90 0xc9 recommended setting. 0x91 0x40 recommended setting. 0x92 0x3c recommended setting. 0x93 0xca recommended setting. 0x94 0xd5 recommended setting. 0xb1 0xff recommended setting. 0xb6 0x08 recommended setting. 0xc0 0x9a recommended setting. 0xcf 0x50 recommended setting. 0xd0 0x4e recommended setting. 0xd1 0xb9 recommended setting. 0xd6 0xdd recommended setting. 0xd7 0xe2 recommended setting. 0xe5 0x51 recommended setting. 0x0e 0x00 recommended setting.
ADV7184 rev. 0 | page 100 of 108 mode 2 s-video input y on ain2 and c on ain3. all standards are supported through autodetect, 8-bit, itu-r bt.656 output on p15 to p8. table 106. mode 2 s-video input register address register value notes 0x1d 0x47 enable 28.63636 mhz crystal mode. 0x3a 0x13 power down adc2 and adc3. 0x3b 0x71 recommended setting. 0x3d 0xa2 mwe enable manual window, color kill threshold to 2. 0x3e 0x6a blm optimization. 0x3f 0xa0 bgb optimization. 0x69 0x03 set sdm_sel to 03 for yc/cvbs auto ain11, ain12. 0xc3 0x32 manually mux y signal on ain2 to adc0 and c signal on ain3 to adc1. 0xc4 0xff manual mux enable. 0xf3 0x03 enable anti-alias filter on adc0 and adc1. 0xf9 0x03 set maximum v lock range. 0x0e 0x80 recommended setting. 0x52 0x46 recommended setting. 0x54 0x00 recommended setting. 0x7f 0xff recommended setting. 0x81 0x30 recommended setting. 0x90 0xc9 recommended setting. 0x91 0x40 recommended setting. 0x92 0x3c recommended setting. 0x93 0xca recommended setting. 0x94 0xd5 recommended setting. 0xb1 0xff recommended setting. 0xb6 0x08 recommended setting. 0xc0 0x9a recommended setting. 0xcf 0x50 recommended setting. 0xd0 0x4e recommended setting. 0xd1 0xb9 recommended setting. 0xd6 0xdd recommended setting. 0xd7 0xe2 recommended setting. 0xe5 0x51 recommended setting. 0x0e 0x00 recommended setting.
ADV7184 rev. 0 | page 101 of 108 mode 3 525i/625i yprpb input y on ain6, pr on ain4, and pb on ain5. all standards are supported through autodetect, 8-bit, itu-r bt.656 output on p15 to p8. table 107. mode 3 yprpb input 525i/625i register address register value notes 0x8d 0x83 recommended setting. 0x00 0x09 set yprpb mode. note: writes below to regist ers 0xc3 and 0xc4, overrides insel yprpb setting. 0x1d 0x47 enable 28.63636 mhz crystal mode. 0x27 0x98 swap cr and cb , y/c delay correction. 0x3a 0x11 power down adc3. 0x3b 0x71 recommended setting. 0x3d 0xa2 mwe enable manual window, color kill threshold to 2. 0x3e 0x6a blm optimization. 0x3f 0xa0 bgb optimization. 0xb4 0xf9 recommended setting. 0xb5 0x00 recommended setting. 0xc3 0x46 manually mux y signal on ain6 to adc0, pr signal on ain4 to adc1. 0xc4 0xb5 manual mux enable, pb signal on ain5 to adc2. 0xf3 0x07 enable anti-alias fi lter on adc0, adc1 and adc2. 0xf9 0x03 set maximum v lock range. 0x0e 0x80 recommended setting. 0x52 0x46 recommended setting. 0x54 0x00 recommended setting. 0x7f 0xff recommended setting. 0x81 0x30 recommended setting. 0x90 0xc9 recommended setting. 0x91 0x40 recommended setting. 0x92 0x3c recommended setting. 0x93 0xca recommended setting. 0x94 0xd5 recommended setting. 0x7e 0x73 recommended setting. 0xb1 0xff recommended setting. 0xb6 0x08 recommended setting. 0xc0 0x9a recommended setting. 0xcf 0x50 recommended setting. 0xd0 0x4e recommended setting. 0xd1 0xb9 recommended setting. 0xd6 0xdd recommended setting. 0xe5 0x51 recommended setting. 0x0e 0x00 recommended setting.
ADV7184 rev. 0 | page 102 of 108 mode 4 scarts-video or cvbs autodetect y/cvbs input on ain11, c input on ain12, 8-bit, itu-r bt.656 output on p15 to p8. table 108. mode 4 scart cvbs/s-video autodetect on ain 11/ ain12 register address register value notes 0x1d 0x47 enable 28.63636 mhz crystal mode. 0x3a 0x13 power down adc2 and adc3. 0x3b 0x71 recommended setting 0x3d 0xa2 mwe enable manual window, color kill threshold to 2. 0x3e 0x6a blm optimization. 0x3f 0xa0 bgb optimization. 0x69 0x03 set sdm_sel to 03 for yc/cvbs auto ain11, ain12. 0xf3 0x03 enable anti-alias filter on adc0 and adc1. 0xf9 0x03 set maximum v lock range 0x0e 0x80 recommended setting. 0x52 0x46 recommended setting. 0x54 0x00 recommended setting. 0x7f 0xff recommended setting. 0x81 0x30 recommended setting. 0x90 0xc9 recommended setting. 0x91 0x40 recommended setting. 0x92 0x3c recommended setting. 0x93 0xca recommended setting. 0x94 0xd5 recommended setting. 0xb1 0xff recommended setting 0xb6 0x08 recommended setting. 0xc0 0x9a recommended setting. 0xcf 0x50 recommended setting. 0xd0 0x4e recommended setting. 0xd1 0xb9 recommended setting. 0xd6 0xdd recommended setting. 0xd7 0xe2 recommended setting. 0xe5 0x51 recommended setting. 0x0e 0x00 recommended setting.
ADV7184 rev. 0 | page 103 of 108 mode 5 scart fast blankcvbs and rgb cvbs input on ain11, b input on ain7, r input on ain8, g input on ain9; 8-bit, itu-r bt.656 output on p15 to p8. table 109. mode 5 scart cvbs/s-video autodetect on ain 11/ ain12 register address register value notes 0x00 0x0f cvbs on ain11. 0x17 0x41 set csfm to sh1. 0x19 0xfa split filter control. 0x1d 0x47 enable 28.63636 mhz crystal mode. 0x3a 0x10 power up all four adcs. 0x3b 0x71 recommended setting. 0x3d 0xa2 mwe enable manual window, color kill threshold to 2. 0x3e 0x6a blm optimization. 0x3f 0xa0 bgb optimization. 0x4d 0xee disable cti 0x67 0x01 format 422. 0x73 0xd0 manual gain channels a, b, c. 0x74 0x04 manual gain channels a, b, c. 0x75 0x01 manual gain channels a, b, c. 0x76 0x00 manual gain channels a, b, c. 0x77 0x04 manual offsets a to 64d, b and c to 512d. 0x78 0x08 manual offsets a to 64d, b and c to 512d. 0x79 0x02 manual offsets a to 64d, b and c to 512d. 0x7a 0x00 manual offsets a to 64d, b and c to 512d. 0xc5 0x00 recommended write. 0xed 0x12 enable dynamic fast blank mode. 0xf3 0x0f enable anti-alias filter on all adcs. 0xf9 0x03 set maximum v lock range. 0x0e 0x80 recommended setting. 0x49 0x01 recommended setting. 0x52 0x46 recommended setting. 0x54 0x00 recommended setting. 0x7f 0xff recommended setting. 0x81 0x30 recommended setting. 0x90 0xc9 recommended setting. 0x91 0x40 recommended setting. 0x92 0x3c recommended setting. 0x93 0xca recommended setting. 0x94 0xd5 recommended setting. 0xb1 0xff recommended setting. 0xb6 0x08 recommended setting. 0xc0 0x9a recommended setting. 0xcf 0x50 recommended setting. 0xd0 0x4e recommended setting. 0xd1 0xb9 recommended setting. 0xd6 0xdd recommended setting. 0xd7 0xe2 recommended setting. 0xe5 0x51 recommended setting. 0x0e 0x00 recommended setting.
ADV7184 rev. 0 | page 104 of 108 mode 6 scart rgb input (static fast blank)cvbs and rgb cvbs input on ain11, b input on ain7, r input on ain8, g input on ain9, 8-bit, itu-r bt.656 output on p15 to p8. table 110. mode 6 scart cvbs/s-video autodetect on ain 11/ ain12 register address register value notes 0x00 0x0f cvbs on ain11. 0x1d 0x47 enable 28.63636 mhz crystal mode. 0x3a 0x10 power up all four adcs. 0x3b 0x71 recommended setting. 0x3d 0xa2 mwe enable manual window, color kill threshold to 2. 0x3e 0x6a blm optimization. 0x3f 0xa0 bgb optimization. 0x4d 0xee disable cti. 0x67 0x01 format 422. 0x73 0xd0 manual gain channels a, b, c. 0x74 0x04 manual gain channels a, b, c. 0x75 0x01 manual gain channels a, b, c. 0x76 0x00 manual gain channels a, b, c. 0x77 0x04 manual offsets a to 64d, b and c to 512d. 0x78 0x08 manual offsets a to 64d, b and c to 512d. 0x79 0x02 manual offsets a to 64d, b and c to 512d. 0x7a 0x00 manual offsets a to 64d, b and c to 512d. 0x93 0x78 clamp optimization 0x94 0x23 clamp optimization 0x95 0x11 clamp optimization 0x96 0xc0 clamp optimization 0xc5 0x00 recommended write. 0xed 0xc4 enable static switchi ng mode and select rgb input. 0xf3 0x0f enable anti-alias filter on all adcs. 0xf9 0x03 set maximum v lock range. 0x0e 0x80 recommended setting. 0x52 0x46 recommended setting. 0x54 0x00 recommended setting. 0x7f 0xff recommended setting. 0x81 0x30 recommended setting. 0x90 0xc9 recommended setting. 0x91 0x40 recommended setting. 0x92 0x3c recommended setting. 0x93 0xca recommended setting. 0x94 0xd5 recommended setting. 0xb1 0xff recommended setting. 0xb6 0x08 recommended setting. 0xc0 0x9a recommended setting. 0xcf 0x50 recommended setting. 0xd0 0x4e recommended setting. 0xd1 0xb9 recommended setting. 0xd6 0xdd recommended setting. 0xd7 0xe2 recommended setting. 0xe5 0x51 recommended setting. 0x0e 0x00 recommended setting.
ADV7184 rev. 0 | page 105 of 108 pcb layout recommendations the ADV7184 is a high precision, high speed mixed-signal device. to achieve the maximum performance from the part, it is important to have a well laid out pcb board. the following is a guide for designing a board using the ADV7184. analog interface inputs care should be taken when routing the inputs on the pcb. track lengths should be kept to a minimum, and 75 trace impedances should be used when possible. trace impedances other than 75 increase the chance of reflections. power supply decoupling it is recommended to decouple each power supply pin with 0.1 f and 10 nf capacitors. the fundamental idea is to have a decoupling capacitor within about 0.5 cm of each power pin. also, avoid placing the capacitor on the opposite side of the pc board from the ADV7184, as doing so interposes resistive vias in the path. the decoupling capacitors should be located between the power plane and the power pin. current should flow from the power plane to the capacitor to the power pin. do not make the power connection between the capacitor and the power pin. placing a via underneath the 100 nf capacitor pads, down to the power plane, is generally the best approach (see figure 47). 05479-051 vdd gnd 10nf 100nf via to supply via to gnd figure 47. recommended power supply decoupling it is particularly important to maintain low noise and good stability of pvdd. careful attention must be paid to regulation, filtering, and decoupling. it is highly desirable to provide separate regulated supplies for each of the analog circuitry groups (avdd, dvdd, dvddio, and pvdd). some graphic controllers use substantially different levels of power when active (during active picture time) and when idle (during horizontal and vertical sync periods). this can result in a measurable change in the voltage supplied to the analog supply regulator, which can, in turn, produce changes in the regulated analog supply voltage. this can be mitigated by regulating the analog supply, or at least pvdd, from a different, cleaner power source, for example, from a 12 v supply. it is also recommended to use a single ground plane for the entire board. this ground plane should have a space between the analog and digital sections of the pcb (see figure 48). 05479-052 analog section digital section ADV7184 figure 48. pcb ground layout experience has repeatedly shown that the noise performance is the same or better with a single ground plane. using multiple ground planes can be detrimental because each separate ground plane is smaller, and long ground loops can result. in some cases, using separate ground planes is unavoidable. for those cases, it is recommended to place a single ground plane under the ADV7184. the location of the split should be under the ADV7184. for this case, it is even more important to place components wisely because the current loops are much longer (current takes the path of least resistance). an example of a current loop: power plane to ADV7184 to digital output trace to digital data receiver to digital ground plane to analog ground plane. pll place the pll loop filter components as close as possible to the elpf pin. do not place any digital or other high frequency traces near these components. use the values suggested in figure 50 with tolerances of 10% or less. digital outputs (both data and clocks) try to minimize the trace length that the digital outputs have to drive. longer traces have higher capacitance, which requires more current, which causes more internal digital noise. shorter traces reduce the possibility of reflections. adding a 30 to 50 series resistor can suppress reflections, reduce emi, and reduce the current spikes inside the ADV7184. if series resistors are used, place them as close as possible to the ADV7184 pins. however, try not to add vias or extra length to the output trace to make the resistors closer. if possible, limit the capacitance that each of the digital outputs drives to less than 15 pf. this can easily be accomplished by keeping traces short and by connecting the outputs to only one device. loading the outputs with excessive capacitance increases the current transients inside the ADV7184, creating more digital noise on its power supplies.
ADV7184 rev. 0 | page 106 of 108 digital inputs the digital inputs on the ADV7184 are designed to work with 3.3 v signals, and are not tolerant of 5 v signals. extra components are needed if 5 v logic signals are required to be applied to the decoder. xtal and load capacitor values selection figure 49 shows an example reference clock circuit for the ADV7184. special care must be taken when using a crystal circuit to generate the reference clock for the ADV7184. small variations in reference clock frequency may cause autodetection issues and impair the ADV7184 performance. c 1 = 47pf c2 = 47pf xtal 28.63636mhz 05479-054 r = 1m figure 49. crystal circuit use the following guidelines to ensure correct operation: ? use the correct, 28.63636 mhz, frequency crystal. tolerance should be 50 ppm or better. ? user a parallel-resonant crystal. ? know the c load for the crystal part selected. the values of the c1 and c2 capacitors must be calculated using this c load value. to find c1 and c2, use the following formula: c = 2( c load ? c stray ) ? c pg where c stra y is usually 2 pf to 3 pf, depending on board traces, and c pg (pin-to-ground capacitance) is 4 pf for the ADV7184. example: c load = 30 pf. c1 = 50 pf, c2 = 50 pf (in this case 47 pf is the nearest real-life cap value to 50 pf)
ADV7184 rev. 0 | page 107 of 108 typical circuit connection an example of how to connect the ADV7184 video decoder is shown in figure 50. for a detailed schematic diagram for the ADV7184, refer to the ADV7184 evaluation note, which can be obtained from a local adi representative. p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 int interrupt o/p p12 sfl sfl o/p p13 hs hs o/p p14 vs vs o/p llc1 27mhz output clock p15 field field o/p llc2 oe 13.5mhz output clock output enable i/p pvdd elpf 10nf 82nf 1.7k dgnd agnd dgnd agnd multiformat pixel port p15?p8 8-bit itu-r bt.656 pixel data @ 27mhz p7?p0 cb and cr 16-bit itu-r bt.656 pixel data @ 13.5mhz p15?p8 y 16-bit itu-r bt.656 pixel data @ 13.5mhz 0.1 f dgnd 0.01 f dgnd 33 f dgnd 10 f dgnd ferrite bead dvddio (3.3v) power supply decoupling for each power pin 0.1 f agnd 0.01 f agnd 33 f agnd 10 f agnd ferrite bead pvdd (1.8v) power supply decoupling for each power pin 0.1 f agnd 0.01 f agnd 33 f agnd 10 f agnd ferrite bead avdd (3.3v) power supply decoupling for each power pin 0.1 f dgnd 0.01 f dgnd 33 f dgnd 10 f dgnd ferrite bead dvdd (1.8v) power supply decoupling for each power pin agnd dgnd dvddio pvdd avdd dvdd fb 100nf ain1 100nf ain7 100nf ain2 100nf ain8 100nf ain3 100nf ain4 100nf ain5 100nf ain11 100nf ain9 100nf ain10 100nf ain6 100nf ain12 56 75 75 75 75 75 56 75 75 56 75 pr pb y cvbs0 cvbs1 s-video y c 19 agnd f_blnk blue red/c green cvbs/y 19 19 agnd 2k 2k + capy1 capy2 agnd 1nf 0.1 f 10 f 0.1 f + capc1 capc2 cml agnd 1nf 0.1 f 10 f 0.1 f dgnd dvddio 100nf + 10 f 0.1 f refout agnd 0.1 f 10 f + xtal 47pf 1 dgnd xtal1 alsb 47pf 1 dgnd 28.6363mhz dvddio select i 2 c address dvss mpu interface control lines sclk sda 100 100 dvddio dvddio 4.7k reset reset 05479-053 ADV7184 1m 1 load cap values are dependent on crystal attributes. figure 50. typical connection diagram
ADV7184 rev. 0 | page 108 of 108 outline dimensions compliant to jedec standards ms-026-bec 1.45 1.40 1.35 0.15 0.05 0.20 0.09 0.10 max coplanarity view a rotated 90 ccw seating plane 7 3.5 0 61 60 1 80 20 41 21 40 view a 1.60 max 0.75 0.60 0.45 16.20 16.00 sq 15.80 14.20 14.00 sq 13.80 0.65 bsc lead pitch 0.38 0.32 0.22 top view (pins down) pin 1 figure 51. 80-lead low profile quad flat package [lqfp] (st-80-2) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ADV7184bstz 2 C40c to +85c low profile quad flat package (lqfp) st-80-2 eval-ADV7184eb evaluation board 1 the ADV7184 is a pb-free, environmentally friendly product. it is man ufactured using the most up -to-date materials and process es. the coating on the leads of each device is 100% pure sn electrop late. the device is suitable fo r pb-free applications, and is ab le to withstand surface-mount so ldering at up to 255c (5c). in addition, it is backward-compatible with conventional snpb soldering processes. this means that the electroplated sn coating can be solde red with snpb solder pastes at conventional reflow temp eratures of 220c to 235c. 2 z = pb-free part. purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05479C0C7/05(0)

▲Up To Search▲

Price & Availability of ADV7184

	To Download ADV7184 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .